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Message-ID: <DM6PR13MB3451F3BECC0B04765B68ED4997370@DM6PR13MB3451.namprd13.prod.outlook.com>
Date: Sat, 26 Sep 2020 04:51:09 +0000
From: Sagar Kadam <sagar.kadam@...nfive.com>
To: Rob Herring <robh@...nel.org>
CC: "linux-pwm@...r.kernel.org" <linux-pwm@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"linux-riscv@...ts.infradead.org" <linux-riscv@...ts.infradead.org>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
"linux-clk@...r.kernel.org" <linux-clk@...r.kernel.org>,
"mturquette@...libre.com" <mturquette@...libre.com>,
"sboyd@...nel.org" <sboyd@...nel.org>,
"Paul Walmsley ( Sifive)" <paul.walmsley@...ive.com>,
"palmer@...belt.com" <palmer@...belt.com>,
"tglx@...utronix.de" <tglx@...utronix.de>,
"jason@...edaemon.net" <jason@...edaemon.net>,
"maz@...nel.org" <maz@...nel.org>,
"thierry.reding@...il.com" <thierry.reding@...il.com>,
"u.kleine-koenig@...gutronix.de" <u.kleine-koenig@...gutronix.de>,
"lee.jones@...aro.org" <lee.jones@...aro.org>,
"aou@...s.berkeley.edu" <aou@...s.berkeley.edu>,
Yash Shah <yash.shah@...nfive.com>
Subject: RE: [PATCH v1 3/3] dt-bindings: riscv: convert pwm bindings to
json-schema
Hello Rob,
> -----Original Message-----
> From: Rob Herring <robh@...nel.org>
> Sent: Wednesday, September 23, 2020 2:07 AM
> To: Sagar Kadam <sagar.kadam@...nfive.com>
> Cc: linux-pwm@...r.kernel.org; linux-kernel@...r.kernel.org; linux-
> riscv@...ts.infradead.org; devicetree@...r.kernel.org; linux-
> clk@...r.kernel.org; mturquette@...libre.com; sboyd@...nel.org; Paul
> Walmsley ( Sifive) <paul.walmsley@...ive.com>; palmer@...belt.com;
> tglx@...utronix.de; jason@...edaemon.net; maz@...nel.org;
> thierry.reding@...il.com; u.kleine-koenig@...gutronix.de;
> lee.jones@...aro.org; aou@...s.berkeley.edu; Yash Shah
> <yash.shah@...nfive.com>
> Subject: Re: [PATCH v1 3/3] dt-bindings: riscv: convert pwm bindings to json-
> schema
>
> [External Email] Do not click links or attachments unless you recognize the
> sender and know the content is safe
>
> On Thu, Sep 10, 2020 at 04:14:04PM +0530, Sagar Kadam wrote:
> > Convert device tree bindings for SiFive's PWM controller to YAML
> > format.
> >
> > Signed-off-by: Sagar Kadam <sagar.kadam@...ive.com>
> > ---
> > .../devicetree/bindings/pwm/pwm-sifive.txt | 33 ----------
> > .../devicetree/bindings/pwm/pwm-sifive.yaml | 72
> ++++++++++++++++++++++
> > 2 files changed, 72 insertions(+), 33 deletions(-) delete mode
> > 100644 Documentation/devicetree/bindings/pwm/pwm-sifive.txt
> > create mode 100644
> > Documentation/devicetree/bindings/pwm/pwm-sifive.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/pwm/pwm-sifive.txt
> > b/Documentation/devicetree/bindings/pwm/pwm-sifive.txt
> > deleted file mode 100644
> > index 3d1dd7b0..0000000
> > --- a/Documentation/devicetree/bindings/pwm/pwm-sifive.txt
> > +++ /dev/null
> > @@ -1,33 +0,0 @@
> > -SiFive PWM controller
> > -
> > -Unlike most other PWM controllers, the SiFive PWM controller
> > currently only -supports one period for all channels in the PWM. All
> > PWMs need to run at -the same period. The period also has significant
> > restrictions on the values -it can achieve, which the driver rounds to the
> nearest achievable period.
> > -PWM RTL that corresponds to the IP block version numbers can be found
> > -here:
> > -
> > -https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/de
> > vices/pwm
> > -
> > -Required properties:
> > -- compatible: Should be "sifive,<chip>-pwm" and "sifive,pwm<version>".
> > - Supported compatible strings are: "sifive,fu540-c000-pwm" for the
> > SiFive
> > - PWM v0 as integrated onto the SiFive FU540 chip, and "sifive,pwm0"
> > for the
> > - SiFive PWM v0 IP block with no chip integration tweaks.
> > - Please refer to sifive-blocks-ip-versioning.txt for details.
> > -- reg: physical base address and length of the controller's registers
> > -- clocks: Should contain a clock identifier for the PWM's parent clock.
> > -- #pwm-cells: Should be 3. See pwm.yaml in this directory
> > - for a description of the cell format.
> > -- interrupts: one interrupt per PWM channel
> > -
> > -Examples:
> > -
> > -pwm: pwm@...20000 {
> > - compatible = "sifive,fu540-c000-pwm", "sifive,pwm0";
> > - reg = <0x0 0x10020000 0x0 0x1000>;
> > - clocks = <&tlclk>;
> > - interrupt-parent = <&plic>;
> > - interrupts = <42 43 44 45>;
> > - #pwm-cells = <3>;
> > -};
> > diff --git a/Documentation/devicetree/bindings/pwm/pwm-sifive.yaml
> > b/Documentation/devicetree/bindings/pwm/pwm-sifive.yaml
> > new file mode 100644
> > index 0000000..415d053
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/pwm/pwm-sifive.yaml
> > @@ -0,0 +1,72 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) # Copyright
> > +(C) 2020 SiFive, Inc.
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/pwm/pwm-sifive.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: SiFive PWM controller
> > +
> > +maintainers:
> > + - Yash Shah <yash.shah@...ive.com>
> > + - Sagar Kadam <sagar.kadam@...ive.com>
> > + - Paul Walmsley <paul.walmsley@...ive.com>
> > +
> > +description:
> > + Unlike most other PWM controllers, the SiFive PWM controller
> > +currently
> > + only supports one period for all channels in the PWM. All PWMs need
> > +to
> > + run at the same period. The period also has significant
> > +restrictions on
> > + the values it can achieve, which the driver rounds to the nearest
> > + achievable period. PWM RTL that corresponds to the IP block version
> > + numbers can be found here -
> > +
> > +
> > + https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/d
> > + evices/pwm
> > +
> > +properties:
> > + compatible:
> > + items:
> > + - const: sifive,fu540-c000-pwm
> > + - const: sifive,pwm0
> > + description:
> > + Should be "sifive,<chip>-pwm" and "sifive,pwm<version>". Supported
> > + compatible strings are "sifive,fu540-c000-pwm" for the SiFive PWM v0
> > + as integrated onto the SiFive FU540 chip, and "sifive,pwm0" for the
> > + SiFive PWM v0 IP block with no chip integration tweaks.
> > + Please refer to sifive-blocks-ip-versioning.txt for details.
> > +
> > + reg:
> > + maxItems: 1
> > + description: Physical base address and length of the controller's
> > + registers
>
> Drop description.
Okay.
>
> > +
> > + clocks:
> > + description: Should contain a clock identifier for the PWM's parent
> clock.
>
> How many clocks?
>
PWM IP block instance is clocked with single clock (tlclk).
> > +
> > + "#pwm-cells":
> > + const: 3
> > + description:
> > + Should be 3. See pwm.yaml in this directory for a description of the
> > + cell format.
>
> Drop.
Okay, I will drop this description.
>
> > +
> > + interrupts:
> > + maxItems: 1
>
> Is it 1 or...
>
> > + description: One interrupt per PWM channel.
>
> one per channel?
>
Each PWM instance in FU540-C000 has 4 independent comparator's
each capable of generating interrupts. So maxItems need to be 4 and I can
include it in description something like:
" description:
Each PWM instance in FU540-C000 has 4 comparators. One interrupt per comparator"
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - clocks
> > + - "#pwm-cells"
> > + - interrupts
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + pwm: pwm@...20000 {
> > + compatible = "sifive,fu540-c000-pwm", "sifive,pwm0";
> > + reg = <0x10020000 0x1000>;
> > + clocks = <&tlclk>;
> > + interrupt-parent = <&plic>;
> > + interrupts = <42 43 44 45>;
>
> Split entries:
>
> interrupts = <42>, <43>, <44>, <45>;
>
Yes, I will split entries as suggested.
Thanks & BR,
Sagar
> > + #pwm-cells = <3>;
> > + };
> > --
> > 2.7.4
> >
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