linux-kernel - Re: [PATCH 1/5] arm64: spe: Allow new bits in SPE filter register

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <20200927025143.GA9677@leoy-ThinkPad-X240s>
Date:   Sun, 27 Sep 2020 10:51:43 +0800
From:   Leo Yan <leo.yan@...aro.org>
To:     Andre Przywara <andre.przywara@....com>
Cc:     Will Deacon <will@...nel.org>,
        Catalin Marinas <catalin.marinas@....com>,
        Peter Zijlstra <peterz@...radead.org>,
        Ingo Molnar <mingo@...hat.com>,
        Arnaldo Carvalho de Melo <acme@...nel.org>,
        Mark Rutland <mark.rutland@....com>,
        Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
        Jiri Olsa <jolsa@...hat.com>,
        Namhyung Kim <namhyung@...nel.org>,
        Suzuki K Poulose <suzuki.poulose@....com>,
        Tan Xiaojun <tanxiaojun@...wei.com>,
        James Clark <james.clark@....com>,
        linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 1/5] arm64: spe: Allow new bits in SPE filter register

Hi Andre,

On Tue, Sep 22, 2020 at 11:12:21AM +0100, Andre Przywara wrote:
> The ARMv8.3-SPE extension adds some new bits for the event filter.
> 
> Remove bits 11, 17 and 18 from the RES0 mask, so they can be used
> correctly.
> 
> Signed-off-by: Andre Przywara <andre.przywara@....com>
> ---
>  arch/arm64/include/asm/sysreg.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index 554a7e8ecb07..efca4ee28671 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -281,7 +281,7 @@
>  #define SYS_PMSFCR_EL1_ST_SHIFT		18
>  
>  #define SYS_PMSEVFR_EL1			sys_reg(3, 0, 9, 9, 5)
> -#define SYS_PMSEVFR_EL1_RES0		0x0000ffff00ff0f55UL
> +#define SYS_PMSEVFR_EL1_RES0		0x0000ffff00f90755UL

This patch is duplicate with Wei Li's patch [1].  You could see there
have some discussion and Will gave suggestions [2] for the patch, this
would be a good start point to continue this work.

Thanks,
Leo

[1] https://www.spinics.net/lists/arm-kernel/msg825364.html
[2] https://www.spinics.net/lists/arm-kernel/msg835733.html

>  
>  #define SYS_PMSLATFR_EL1		sys_reg(3, 0, 9, 9, 6)
>  #define SYS_PMSLATFR_EL1_MINLAT_SHIFT	0
> -- 
> 2.17.1
>