linux-kernel - Re: [PATCH v4 00/10] Support qcom USB3+DP combo phy (or type-c phy)

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Date:   Mon, 28 Sep 2020 11:28:19 +0530
From:   Vinod Koul <vkoul@...nel.org>
To:     Stephen Boyd <swboyd@...omium.org>
Cc:     Kishon Vijay Abraham I <kishon@...com>,
        linux-kernel@...r.kernel.org, linux-arm-msm@...r.kernel.org,
        Jeykumar Sankaran <jsanka@...eaurora.org>,
        Chandan Uddaraju <chandanu@...eaurora.org>,
        Vara Reddy <varar@...eaurora.org>,
        Tanmay Shah <tanmay@...eaurora.org>,
        Bjorn Andersson <bjorn.andersson@...aro.org>,
        Manu Gautam <mgautam@...eaurora.org>,
        Sandeep Maheswaram <sanm@...eaurora.org>,
        Douglas Anderson <dianders@...omium.org>,
        Sean Paul <seanpaul@...omium.org>,
        Rob Clark <robdclark@...omium.org>,
        Jonathan Marek <jonathan@...ek.ca>,
        Dmitry Baryshkov <dmitry.baryshkov@...aro.org>,
        devicetree@...r.kernel.org, Rob Herring <robh+dt@...nel.org>,
        Stephen Boyd <sboyd@...nel.org>
Subject: Re: [PATCH v4 00/10] Support qcom USB3+DP combo phy (or type-c phy)

On 16-09-20, 16:11, Stephen Boyd wrote:
> This patch series is based on v12 of the msm DP driver submission[1]
> plus a compliance patch[2]. In the v5 patch series review I suggested
> that the DP PHY and PLL be split out of the drm driver and moved to the
> qmp phy driver. This patch series does that, but it is still marked as
> an RFC because there are a couple more things to do, mostly updating the
> DT binding and getting agreement on how to structure the code.
> 
> Eventually I believe the qmp phy driver will need to listen for type-c
> notifiers or somehow know the type-c pinout being used so this driver
> can program things slightly differently. Right now, I don't have any way
> to test it though, so I've left it as future work. For some more
> details, the DP phy and the USB3 phy share the same physical pins on the
> SoC and those pins pretty much line up with a type-c pinout modulo some
> CC pins for cable orientation detection logic that lives on the PMIC. So
> the DP phy can use all four lanes or it can use two lanes and the USB3
> phy can use two lanes. In the hardware designs that I have access to it
> is always two lanes for USB3 and two lanes for DP going through what
> looks like a type-c pinout so this just hard codes that configuration in
> the driver.

Applied 1 thru 8, thanks

-- 
~Vinod