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Message-Id: <1601274460-7866-4-git-send-email-kevin3.tang@gmail.com>
Date: Mon, 28 Sep 2020 14:27:37 +0800
From: Kevin Tang <kevin3.tang@...il.com>
To: maarten.lankhorst@...ux.intel.com, mripard@...nel.org,
sean@...rly.run, airlied@...ux.ie, daniel@...ll.ch,
robh+dt@...nel.org, mark.rutland@....com, kevin3.tang@...il.com
Cc: orsonzhai@...il.com, zhang.lyra@...il.com,
linux-kernel@...r.kernel.org, dri-devel@...ts.freedesktop.org
Subject: [PATCH RFC v7 3/6] dt-bindings: display: add Unisoc's dpu bindings
From: Kevin Tang <kevin.tang@...soc.com>
DPU (Display Processor Unit) is the Display Controller for the Unisoc SoCs
which transfers the image data from a video memory buffer to an internal
LCD interface.
RFC v7:
- Fix DTC unit name warnings
- Fix the problem of maintainers
Cc: Orson Zhai <orsonzhai@...il.com>
Cc: Chunyan Zhang <zhang.lyra@...il.com>
Signed-off-by: Kevin Tang <kevin.tang@...soc.com>
---
.../bindings/display/sprd/sprd,sharkl3-dpu.yaml | 83 ++++++++++++++++++++++
1 file changed, 83 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/sprd/sprd,sharkl3-dpu.yaml
diff --git a/Documentation/devicetree/bindings/display/sprd/sprd,sharkl3-dpu.yaml b/Documentation/devicetree/bindings/display/sprd/sprd,sharkl3-dpu.yaml
new file mode 100644
index 0000000..a9052e1
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/sprd/sprd,sharkl3-dpu.yaml
@@ -0,0 +1,83 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/sprd/sprd,sharkl3-dpu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Unisoc Sharkl3 Display Processor Unit (DPU)
+
+maintainers:
+ - Kevin Tang <kevin.tang@...soc.com>
+
+description: |
+ DPU (Display Processor Unit) is the Display Controller for the Unisoc SoCs
+ which transfers the image data from a video memory buffer to an internal
+ LCD interface.
+
+properties:
+ compatible:
+ const: sprd,sharkl3-dpu
+
+ reg:
+ maxItems: 1
+ description:
+ Physical base address and length of the DPU registers set
+
+ interrupts:
+ maxItems: 1
+ description:
+ The interrupt signal from DPU
+
+ clocks:
+ minItems: 2
+
+ clock-names:
+ items:
+ - const: clk_src_128m
+ - const: clk_src_384m
+
+ power-domains:
+ maxItems: 1
+ description: A phandle to DPU power domain node.
+
+ iommus:
+ maxItems: 1
+ description: A phandle to DPU iommu node.
+
+ port:
+ type: object
+ description:
+ A port node with endpoint definitions as defined in
+ Documentation/devicetree/bindings/media/video-interfaces.txt.
+ That port should be the output endpoint, usually output to
+ the associated DSI.
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - port
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/sprd,sc9860-clk.h>
+ dpu: dpu@...00000 {
+ compatible = "sprd,sharkl3-dpu";
+ reg = <0x63000000 0x1000>;
+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "clk_src_128m", "clk_src_384m";
+
+ clocks = <&pll CLK_TWPLL_128M>,
+ <&pll CLK_TWPLL_384M>;
+
+ dpu_port: port {
+ dpu_out: endpoint {
+ remote-endpoint = <&dsi_in>;
+ };
+ };
+ };
--
2.7.4
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