linux-kernel - Re: [PATCH net v4] net: phy: realtek: fix rtl8211e rx/tx delay config

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Message-Id: <20200929.125632.1592891495047804335.davem@davemloft.net>
Date:   Tue, 29 Sep 2020 12:56:32 -0700 (PDT)
From:   David Miller <davem@...emloft.net>
To:     willy.liu@...ltek.com
Cc:     andrew@...n.ch, hkallweit1@...il.com, linux@...linux.org.uk,
        kuba@...nel.org, fancer.lancer@...il.com, netdev@...r.kernel.org,
        linux-kernel@...r.kernel.org, kevans@...eBSD.org,
        ryankao@...ltek.com
Subject: Re: [PATCH net v4] net: phy: realtek: fix rtl8211e rx/tx delay
 config

From: Willy Liu <willy.liu@...ltek.com>
Date: Tue, 29 Sep 2020 10:10:49 +0800

> There are two chip pins named TXDLY and RXDLY which actually adds the 2ns
> delays to TXC and RXC for TXD/RXD latching. These two pins can config via
> 4.7k-ohm resistor to 3.3V hw setting, but also config via software setting
> (extension page 0xa4 register 0x1c bit13 12 and 11).
> 
> The configuration register definitions from table 13 official PHY datasheet:
> PHYAD[2:0] = PHY Address
> AN[1:0] = Auto-Negotiation
> Mode = Interface Mode Select
> RX Delay = RX Delay
> TX Delay = TX Delay
> SELRGV = RGMII/GMII Selection
> 
> This table describes how to config these hw pins via external pull-high or pull-
> low resistor.
> 
> It is a misunderstanding that mapping it as register bits below:
> 8:6 = PHY Address
> 5:4 = Auto-Negotiation
> 3 = Interface Mode Select
> 2 = RX Delay
> 1 = TX Delay
> 0 = SELRGV
> So I removed these descriptions above and add related settings as below:
> 14 = reserved
> 13 = force Tx RX Delay controlled by bit12 bit11
> 12 = Tx Delay
> 11 = Rx Delay
> 10:0 = Test && debug settings reserved by realtek
> 
> Test && debug settings are not recommend to modify by default.
> 
> Fixes: f81dadbcf7fd ("net: phy: realtek: Add rtl8211e rx/tx delays config")
> Signed-off-by: Willy Liu <willy.liu@...ltek.com>

Applied and queued up for -stable, thank you.