[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <1289d193-7c69-e93d-f6dd-287cba0f476a@axentia.se>
Date: Tue, 29 Sep 2020 08:24:15 +0200
From: Peter Rosin <peda@...ntia.se>
To: Roger Quadros <rogerq@...com>, nm@...com
Cc: t-kristo@...com, nsekhar@...com, kishon@...com, robh+dt@...nel.org,
devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH v4 1/6] dt-bindings: ti-serdes-mux: Add defines for J7200
SoC
Hi!
On 2020-09-21 16:39, Roger Quadros wrote:
> There are 4 lanes in each J7200 SERDES. Each SERDES lane mux can
> select upto 4 different IPs. Define all the possible functions.
>
> Cc: Peter Rosin <peda@...ntia.se>
> Signed-off-by: Roger Quadros <rogerq@...com>
Acked-by: Peter Rosin <peda@...ntia.se>
Thanks for taking care of this!
Cheers,
Peter
> ---
> include/dt-bindings/mux/ti-serdes.h | 22 ++++++++++++++++++++++
> 1 file changed, 22 insertions(+)
>
> diff --git a/include/dt-bindings/mux/ti-serdes.h b/include/dt-bindings/mux/ti-serdes.h
> index 146d0685a925..9047ec6bd3cf 100644
> --- a/include/dt-bindings/mux/ti-serdes.h
> +++ b/include/dt-bindings/mux/ti-serdes.h
> @@ -68,4 +68,26 @@
> #define J721E_SERDES4_LANE3_QSGMII_LANE8 0x2
> #define J721E_SERDES4_LANE3_IP4_UNUSED 0x3
>
> +/* J7200 */
> +
> +#define J7200_SERDES0_LANE0_QSGMII_LANE3 0x0
> +#define J7200_SERDES0_LANE0_PCIE1_LANE0 0x1
> +#define J7200_SERDES0_LANE0_IP3_UNUSED 0x2
> +#define J7200_SERDES0_LANE0_IP4_UNUSED 0x3
> +
> +#define J7200_SERDES0_LANE1_QSGMII_LANE4 0x0
> +#define J7200_SERDES0_LANE1_PCIE1_LANE1 0x1
> +#define J7200_SERDES0_LANE1_IP3_UNUSED 0x2
> +#define J7200_SERDES0_LANE1_IP4_UNUSED 0x3
> +
> +#define J7200_SERDES0_LANE2_QSGMII_LANE1 0x0
> +#define J7200_SERDES0_LANE2_PCIE1_LANE2 0x1
> +#define J7200_SERDES0_LANE2_IP3_UNUSED 0x2
> +#define J7200_SERDES0_LANE2_IP4_UNUSED 0x3
> +
> +#define J7200_SERDES0_LANE3_QSGMII_LANE2 0x0
> +#define J7200_SERDES0_LANE3_PCIE1_LANE3 0x1
> +#define J7200_SERDES0_LANE3_USB 0x2
> +#define J7200_SERDES0_LANE3_IP4_UNUSED 0x3
> +
> #endif /* _DT_BINDINGS_MUX_TI_SERDES */
>
Powered by blists - more mailing lists