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Message-ID: <20200929144417.89816-12-alexandru.ardelean@analog.com>
Date: Tue, 29 Sep 2020 17:44:13 +0300
From: Alexandru Ardelean <alexandru.ardelean@...log.com>
To: <linux-clk@...r.kernel.org>, <linux-fpga@...r.kernel.org>,
<linux-kernel@...r.kernel.org>
CC: <mturquette@...libre.com>, <sboyd@...nel.org>, <mdf@...nel.org>,
<ardeleanalex@...il.com>, Dragos Bogdan <dragos.bogdan@...log.com>,
"Alexandru Ardelean" <alexandru.ardelean@...log.com>
Subject: [PATCH v4 3/7] clk: axi-clkgen: add support for ZynqMP (UltraScale)
From: Dragos Bogdan <dragos.bogdan@...log.com>
This IP core also works and is supported on the Xilinx ZynqMP (UltraScale)
FPGA boards.
This patch enables the driver to be available on these platforms as well.
Signed-off-by: Dragos Bogdan <dragos.bogdan@...log.com>
Signed-off-by: Alexandru Ardelean <alexandru.ardelean@...log.com>
---
drivers/clk/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index b41aaed9bd51..6d76591c0bc4 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -239,7 +239,7 @@ config CLK_TWL6040
config COMMON_CLK_AXI_CLKGEN
tristate "AXI clkgen driver"
- depends on ARCH_ZYNQ || MICROBLAZE || COMPILE_TEST
+ depends on ARCH_ZYNQ || ARCH_ZYNQMP || MICROBLAZE || COMPILE_TEST
help
Support for the Analog Devices axi-clkgen pcore clock generator for Xilinx
FPGAs. It is commonly used in Analog Devices' reference designs.
--
2.17.1
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