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Date: Wed, 30 Sep 2020 09:38:23 -0700 From: Nathan Chancellor <natechancellor@...il.com> To: Maxime Ripard <maxime@...no.tech> Cc: Nicolas Saenz Julienne <nsaenzjulienne@...e.de>, Eric Anholt <eric@...olt.net>, Stefan Wahren <stefan.wahren@...e.com>, Tim Gover <tim.gover@...pberrypi.com>, Dave Stevenson <dave.stevenson@...pberrypi.com>, linux-kernel@...r.kernel.org, dri-devel@...ts.freedesktop.org, Hoegeun Kwon <hoegeun.kwon@...sung.com>, Chanwoo Choi <cw00.choi@...sung.com>, bcm-kernel-feedback-list@...adcom.com, linux-rpi-kernel@...ts.infradead.org, Phil Elwell <phil@...pberrypi.com>, linux-arm-kernel@...ts.infradead.org Subject: Re: [PATCH v5 80/80] ARM: dts: bcm2711: Enable the display pipeline On Wed, Sep 30, 2020 at 04:07:58PM +0200, Maxime Ripard wrote: > Hi Nathan, > > On Tue, Sep 29, 2020 at 03:15:26PM -0700, Nathan Chancellor wrote: > > On Thu, Sep 03, 2020 at 10:01:52AM +0200, Maxime Ripard wrote: > > > Now that all the drivers have been adjusted for it, let's bring in the > > > necessary device tree changes. > > > > > > The VEC and PV3 are left out for now, since it will require a more specific > > > clock setup. > > > > > > Reviewed-by: Dave Stevenson <dave.stevenson@...pberrypi.com> > > > Tested-by: Chanwoo Choi <cw00.choi@...sung.com> > > > Tested-by: Hoegeun Kwon <hoegeun.kwon@...sung.com> > > > Tested-by: Stefan Wahren <stefan.wahren@...e.com> > > > Signed-off-by: Maxime Ripard <maxime@...no.tech> > > > > Apologies if this has already been reported or have a solution but this > > patch (and presumably series) breaks output to the serial console after > > a certain point during init. On Raspbian, I see systemd startup messages > > then the output just turns into complete garbage. It looks like this > > patch is merged first in linux-next, which is why my bisect fell on the > > DRM merge. I am happy to provide whatever information could be helpful > > for debugging this. I am on the latest version of the firmware > > (currently 26620cc9a63c6cb9965374d509479b4ee2c30241). > > Unfortunately, the miniUART is in the same clock tree than the core > clock and will thus have those kind of issues when the core clock is > changed (which is also something that one should expect when using the > DRM or other drivers). > > The only real workaround there would be to switch to one of the PL011 > UARTs. I guess we can also somehow make the UART react to the core clock > frequency changes, but that's going to require some effort > > Maxime Ack, thank you for the reply! There does not really seem to be a whole ton of documentation around using one of the other PL011 UARTs so for now, I will just revert this commit locally. Cheers, Nathan
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