linux-kernel - RE: [PATCH v2] PCI: Cadence: Add quirk for Gen2 controller to do autonomous speed change.

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Message-ID: <SN2PR07MB25577CF3F0F2B51E14AF34AAD8330@SN2PR07MB2557.namprd07.prod.outlook.com>
Date:   Wed, 30 Sep 2020 16:58:32 +0000
From:   Athani Nadeem Ladkhan <nadeem@...ence.com>
To:     Rob Herring <robh@...nel.org>
CC:     Tom Joseph <tjoseph@...ence.com>,
        Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
        Bjorn Helgaas <bhelgaas@...gle.com>,
        PCI <linux-pci@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        Kishon Vijay Abraham I <kishon@...com>,
        Milind Parab <mparab@...ence.com>,
        Swapnil Kashinath Jakhade <sjakhade@...ence.com>
Subject: RE: [PATCH v2] PCI: Cadence: Add quirk for Gen2 controller to do
 autonomous speed change.

Hi Rob,

> -----Original Message-----
> From: Rob Herring <robh@...nel.org>
> Sent: Thursday, September 24, 2020 1:16 AM
> To: Athani Nadeem Ladkhan <nadeem@...ence.com>
> Cc: Tom Joseph <tjoseph@...ence.com>; Lorenzo Pieralisi
> <lorenzo.pieralisi@....com>; Bjorn Helgaas <bhelgaas@...gle.com>; PCI
> <linux-pci@...r.kernel.org>; linux-kernel@...r.kernel.org; Kishon Vijay
> Abraham I <kishon@...com>; Milind Parab <mparab@...ence.com>;
> Swapnil Kashinath Jakhade <sjakhade@...ence.com>
> Subject: Re: [PATCH v2] PCI: Cadence: Add quirk for Gen2 controller to do
> autonomous speed change.
> 
> EXTERNAL MAIL
> 
> 
> On Wed, Sep 23, 2020 at 12:34 PM Nadeem Athani <nadeem@...ence.com>
> wrote:
> >
> > Cadence controller will not initiate autonomous speed change if
> > strapped as Gen2. The Retrain bit is set as a quirk to trigger this
> > speed change.
> >
> > Signed-off-by: Nadeem Athani <nadeem@...ence.com>
> > ---
> >  drivers/pci/controller/cadence/pcie-cadence-host.c | 14 ++++++++++++++
> >  drivers/pci/controller/cadence/pcie-cadence.h      | 15 +++++++++++++++
> >  2 files changed, 29 insertions(+)
> >
> > diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c
> > b/drivers/pci/controller/cadence/pcie-cadence-host.c
> > index 4550e0d469ca..a2317614268d 100644
> > --- a/drivers/pci/controller/cadence/pcie-cadence-host.c
> > +++ b/drivers/pci/controller/cadence/pcie-cadence-host.c
> > @@ -83,6 +83,9 @@ static int cdns_pcie_host_init_root_port(struct
> cdns_pcie_rc *rc)
> >         struct cdns_pcie *pcie = &rc->pcie;
> >         u32 value, ctrl;
> >         u32 id;
> > +       u32 link_cap = CDNS_PCIE_LINK_CAP_OFFSET;
> > +       u8 sls;
> > +       u16 lnk_ctl;
> >
> >         /*
> >          * Set the root complex BAR configuration register:
> > @@ -111,6 +114,17 @@ static int cdns_pcie_host_init_root_port(struct
> cdns_pcie_rc *rc)
> >         if (rc->device_id != 0xffff)
> >                 cdns_pcie_rp_writew(pcie, PCI_DEVICE_ID,
> > rc->device_id);
> >
> > +       /* Quirk to enable autonomous speed change for GEN2 controller */
> > +       /* Reading Supported Link Speed value */
> > +       sls = PCI_EXP_LNKCAP_SLS &
> > +               cdns_pcie_rp_readb(pcie, link_cap + PCI_EXP_LNKCAP);
> 
> A 32-bit register, right?
Right, this will be corrected in patch version 3.
> 
> > +       if (sls == PCI_EXP_LNKCAP_SLS_5_0GB) {
> > +               /* Since this a Gen2 controller, set Retrain Link(RL) bit */
> > +               lnk_ctl = cdns_pcie_rp_readw(pcie, link_cap + PCI_EXP_LNKCTL);
> > +               lnk_ctl |= PCI_EXP_LNKCTL_RL;
> > +               cdns_pcie_rp_writew(pcie, link_cap + PCI_EXP_LNKCTL, lnk_ctl);
> > +       }
> > +
> >         cdns_pcie_rp_writeb(pcie, PCI_CLASS_REVISION, 0);
> >         cdns_pcie_rp_writeb(pcie, PCI_CLASS_PROG, 0);
> >         cdns_pcie_rp_writew(pcie, PCI_CLASS_DEVICE,
> > PCI_CLASS_BRIDGE_PCI); diff --git
> > a/drivers/pci/controller/cadence/pcie-cadence.h
> > b/drivers/pci/controller/cadence/pcie-cadence.h
> > index feed1e3038f4..fe560480c573 100644
> > --- a/drivers/pci/controller/cadence/pcie-cadence.h
> > +++ b/drivers/pci/controller/cadence/pcie-cadence.h
> > @@ -120,6 +120,7 @@
> >   */
> >  #define CDNS_PCIE_RP_BASE      0x00200000
> >
> > +#define CDNS_PCIE_LINK_CAP_OFFSET 0xC0
> >
> >  /*
> >   * Address Translation Registers
> > @@ -413,6 +414,20 @@ static inline void cdns_pcie_rp_writew(struct
> cdns_pcie *pcie,
> >         cdns_pcie_write_sz(addr, 0x2, value);  }
> >
> > +static inline u8 cdns_pcie_rp_readb(struct cdns_pcie *pcie, u32 reg)
> > +{
> > +       void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg;
> > +
> > +       return cdns_pcie_read_sz(addr, 0x1); }
> > +
> > +static inline u16 cdns_pcie_rp_readw(struct cdns_pcie *pcie, u32 reg)
> > +{
> > +       void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg;
> > +
> > +       return cdns_pcie_read_sz(addr, 0x2); }
> > +
> >  /* Endpoint Function register access */  static inline void
> > cdns_pcie_ep_fn_writeb(struct cdns_pcie *pcie, u8 fn,
> >                                           u32 reg, u8 value)
> > --
> > 2.15.0
> >