linux-kernel - [tip: perf/core] perf/x86/intel: Add Jasper Lake support

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Message-ID: <160149233427.7002.10751745017528986245.tip-bot2@tip-bot2>
Date:   Wed, 30 Sep 2020 18:58:54 -0000
From:   "tip-bot2 for Kan Liang" <tip-bot2@...utronix.de>
To:     linux-tip-commits@...r.kernel.org
Cc:     Kan Liang <kan.liang@...ux.intel.com>,
        "Peter Zijlstra (Intel)" <peterz@...radead.org>,
        x86 <x86@...nel.org>, LKML <linux-kernel@...r.kernel.org>
Subject: [tip: perf/core] perf/x86/intel: Add Jasper Lake support

The following commit has been merged into the perf/core branch of tip:

Commit-ID:     dbfd638889a0396f5fe14ff3cc2263ec1e1cac62
Gitweb:        https://git.kernel.org/tip/dbfd638889a0396f5fe14ff3cc2263ec1e1cac62
Author:        Kan Liang <kan.liang@...ux.intel.com>
AuthorDate:    Mon, 28 Sep 2020 05:30:41 -07:00
Committer:     Peter Zijlstra <peterz@...radead.org>
CommitterDate: Tue, 29 Sep 2020 09:57:01 +02:00

perf/x86/intel: Add Jasper Lake support

The Jasper Lake processor is also a Tremont microarchitecture. From the
perspective of Intel PMU, there is nothing changed compared with
Elkhart Lake.
Share the perf code with Elkhart Lake.

Signed-off-by: Kan Liang <kan.liang@...ux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@...radead.org>
Link: https://lkml.kernel.org/r/1601296242-32763-1-git-send-email-kan.liang@linux.intel.com
---
 arch/x86/events/intel/core.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index c72e490..75dea67 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -5135,6 +5135,7 @@ __init int intel_pmu_init(void)
 
 	case INTEL_FAM6_ATOM_TREMONT_D:
 	case INTEL_FAM6_ATOM_TREMONT:
+	case INTEL_FAM6_ATOM_TREMONT_L:
 		x86_pmu.late_ack = true;
 		memcpy(hw_cache_event_ids, glp_hw_cache_event_ids,
 		       sizeof(hw_cache_event_ids));