linux-kernel - [PATCH v5 2/6] arm64: dts: ti: k3-j7200-main: Add SERDES lane control mux

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Message-ID: <20200930122032.23481-3-rogerq@ti.com>
Date:   Wed, 30 Sep 2020 15:20:28 +0300
From:   Roger Quadros <rogerq@...com>
To:     <nm@...com>
CC:     <t-kristo@...com>, <nsekhar@...com>, <kishon@...com>,
        <devicetree@...r.kernel.org>,
        <linux-arm-kernel@...ts.infradead.org>,
        <linux-kernel@...r.kernel.org>, Roger Quadros <rogerq@...com>
Subject: [PATCH v5 2/6] arm64: dts: ti: k3-j7200-main: Add SERDES lane control mux

The SERDES lane control mux registers are present in the
CTRLMMR space.

Signed-off-by: Roger Quadros <rogerq@...com>
Reviewed-by: Vignesh Raghavendra <vigneshr@...com>
---
 arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
index 4a4fcd24f852..8997276158ca 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
@@ -18,6 +18,21 @@
 		};
 	};
 
+	scm_conf: scm-conf@...000 {
+		compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
+		reg = <0x00 0x00100000 0x00 0x1c000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x00 0x00 0x00100000 0x1c000>;
+
+		serdes_ln_ctrl: serdes-ln-ctrl@...0 {
+			compatible = "mmio-mux";
+			#mux-control-cells = <1>;
+			mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
+					<0x4088 0x3>, <0x408c 0x3>; /* SERDES0 lane2/3 select */
+		};
+	};
+
 	gic500: interrupt-controller@...0000 {
 		compatible = "arm,gic-v3";
 		#address-cells = <2>;
-- 
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