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Message-ID: <CAAvKZ65qyKDrmzHR=HELJmrRdchJ8MEXJZJGcj1oyNXg-BamZA@mail.gmail.com>
Date: Thu, 1 Oct 2020 20:45:45 +0100
From: Tim Gover <tim.gover@...pberrypi.com>
To: Nicolas Saenz Julienne <nsaenzjulienne@...e.de>
Cc: Maxime Ripard <maxime@...no.tech>,
Stefan Wahren <stefan.wahren@...e.com>,
Nathan Chancellor <natechancellor@...il.com>,
Eric Anholt <eric@...olt.net>,
Dave Stevenson <dave.stevenson@...pberrypi.com>,
linux-kernel@...r.kernel.org, dri-devel@...ts.freedesktop.org,
Hoegeun Kwon <hoegeun.kwon@...sung.com>,
Chanwoo Choi <cw00.choi@...sung.com>,
bcm-kernel-feedback-list@...adcom.com,
linux-rpi-kernel@...ts.infradead.org,
Phil Elwell <phil@...pberrypi.com>,
linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH v5 80/80] ARM: dts: bcm2711: Enable the display pipeline
Sorry, my previous statement was misleading.
enable_uart will select the mini_uart for gpio14,15 unless the
disable-bt device tree overlay is loaded. As well as disabling
bluetooth disable-bt swaps the uart0 pin configs to point the regular
UART to gpio 14,15. After resolving the DT overlays the firmware does
the initial UART setup according to which controller is pointed at
pins 14,15.
I'll have to speak to others about exactly when the fixing of the core
clock takes effect. There have been a few changes related to the
initial turbo frequency configuration and how this is reported via the
mbox APIs
On Thu, 1 Oct 2020 at 17:47, Nicolas Saenz Julienne
<nsaenzjulienne@...e.de> wrote:
>
> Hi Tim, thanks for the info!
>
> On Thu, 2020-10-01 at 11:15 +0100, Tim Gover wrote:
> > hdmi_enable_4k60=1 causes the firmware to select 3.3 GHz for the PLLC
> > VCO to support a core-frequency of 550 MHz which is the minimum
> > frequency required by the HVS at 4Kp60. The side effect is that if the
> > display clock requirements are lower than 4Kp60 then you will see
> > different core frequencies selected by DVFS.
> >
> > If enable_uart=1 and the mini-uart is selected (default unless
>
> What is the actual test made to check if mini-uart is selected? I can't get
> firmware to trigger this behaviour with 64-bit upstream kernel/dts. Note that I
> see the core clk setup at 200MHz just before having VC4 set it to 500MHz.
>
> The only thing I've got on my config.txt is:
>
> enable_uart=1
> arm_64bit=1
>
> Maybe we're missing some kind of DT alias upstream?
>
> Regards,
> Nicolas
>
> > bluetooth is disabled) then the firmware will pin the core-frequency
> > to either core_freq max (500 or 550). Although, I think there is a way
> > of pinning it to a lower fixed frequency.
> >
> > The table in overclocking.md defines options for setting the maximum
> > core frequency but unless core_freq_min is specified DVFS will
> > automatically pick the lowest idle frequency required by the display
> > resolution.
>
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