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Message-ID: <915f2c88-1832-3c15-09ee-b0959e0ae70c@microchip.com>
Date: Thu, 1 Oct 2020 13:21:30 +0000
From: <Tudor.Ambarus@...rochip.com>
To: <michael@...le.cc>, <linux-mtd@...ts.infradead.org>,
<linux-arm-kernel@...ts.infradead.org>,
<linux-kernel@...r.kernel.org>
CC: <miquel.raynal@...tlin.com>, <richard@....at>, <vigneshr@...com>
Subject: Re: [RFC PATCH 1/2] mtd: spi-nor: atmel: remove global
SNOR_F_HAS_LOCK
On 10/1/20 3:28 PM, Michael Walle wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> This is considered bad for the following reasons:
> (1) We only support the block protection with BPn bits for write
> protection. Not all Atmel parts support this.
> (2) Newly added flash chip will automatically inherit the "has
> locking" support and thus needs to explicitly tested. Better
> be opt-in instead of opt-out.
> (3) There are already supported flashes which don't support the locking
> scheme. So I assume this wasn't properly tested before adding that
> chip; which enforces my previous argument that locking support should
> be an opt-in.
>
> Remove the global flag and add individual flags to all flashes
> which supports BP locking. In particular the following flashes
> don't support the BP scheme:
> - AT26F004
> - AT25SL321
> - AT45DB081D
>
I like the idea. Thanks for the effort. Will check all those datasheets
and get back to you.
> Signed-off-by: Michael Walle <michael@...le.cc>
> ---
> drivers/mtd/spi-nor/atmel.c | 28 +++++++++-------------------
> 1 file changed, 9 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/mtd/spi-nor/atmel.c b/drivers/mtd/spi-nor/atmel.c
> index 3f5f21a473a6..49d392c6c8bc 100644
> --- a/drivers/mtd/spi-nor/atmel.c
> +++ b/drivers/mtd/spi-nor/atmel.c
> @@ -10,37 +10,27 @@
>
> static const struct flash_info atmel_parts[] = {
> /* Atmel -- some are (confusingly) marketed as "DataFlash" */
> - { "at25fs010", INFO(0x1f6601, 0, 32 * 1024, 4, SECT_4K) },
> - { "at25fs040", INFO(0x1f6604, 0, 64 * 1024, 8, SECT_4K) },
> + { "at25fs010", INFO(0x1f6601, 0, 32 * 1024, 4, SECT_4K | SPI_NOR_HAS_LOCK) },
> + { "at25fs040", INFO(0x1f6604, 0, 64 * 1024, 8, SECT_4K | SPI_NOR_HAS_LOCK) },
>
> - { "at25df041a", INFO(0x1f4401, 0, 64 * 1024, 8, SECT_4K) },
> - { "at25df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K) },
> - { "at25df321a", INFO(0x1f4701, 0, 64 * 1024, 64, SECT_4K) },
> - { "at25df641", INFO(0x1f4800, 0, 64 * 1024, 128, SECT_4K) },
> + { "at25df041a", INFO(0x1f4401, 0, 64 * 1024, 8, SECT_4K | SPI_NOR_HAS_LOCK) },
> + { "at25df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_HAS_LOCK) },
> + { "at25df321a", INFO(0x1f4701, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_HAS_LOCK) },
> + { "at25df641", INFO(0x1f4800, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_HAS_LOCK) },
>
> { "at25sl321", INFO(0x1f4216, 0, 64 * 1024, 64,
> SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
>
> { "at26f004", INFO(0x1f0400, 0, 64 * 1024, 8, SECT_4K) },
> - { "at26df081a", INFO(0x1f4501, 0, 64 * 1024, 16, SECT_4K) },
> - { "at26df161a", INFO(0x1f4601, 0, 64 * 1024, 32, SECT_4K) },
> - { "at26df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K) },
> + { "at26df081a", INFO(0x1f4501, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_HAS_LOCK) },
> + { "at26df161a", INFO(0x1f4601, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_HAS_LOCK) },
> + { "at26df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_HAS_LOCK) },
>
> { "at45db081d", INFO(0x1f2500, 0, 64 * 1024, 16, SECT_4K) },
> };
>
> -static void atmel_default_init(struct spi_nor *nor)
> -{
> - nor->flags |= SNOR_F_HAS_LOCK;
> -}
> -
> -static const struct spi_nor_fixups atmel_fixups = {
> - .default_init = atmel_default_init,
> -};
> -
> const struct spi_nor_manufacturer spi_nor_atmel = {
> .name = "atmel",
> .parts = atmel_parts,
> .nparts = ARRAY_SIZE(atmel_parts),
> - .fixups = &atmel_fixups,
> };
> --
> 2.20.1
>
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