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Message-Id: <20201001152148.29747-8-l.stelmach@samsung.com>
Date: Thu, 1 Oct 2020 17:21:46 +0200
From: Łukasz Stelmach <l.stelmach@...sung.com>
To: Kukjin Kim <kgene@...nel.org>,
Krzysztof Kozlowski <krzk@...nel.org>,
Tomasz Figa <tomasz.figa@...il.com>,
Andi Shyti <andi@...zian.org>, Mark Brown <broonie@...nel.org>,
linux-spi@...r.kernel.org, linux-samsung-soc@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org
Cc: m.szyprowski@...sung.com, b.zolnierkie@...sung.com,
Łukasz Stelmach <l.stelmach@...sung.com>
Subject: [PATCH v2 RESEND 7/9] spi: spi-s3c64xx: Ensure cur_speed holds
actual clock value
Make sure the cur_speed value used in s3c64xx_enable_datapath()
to configure DMA channel and in s3c64xx_wait_for_*() to calculate the
transfer timeout is set to the actual value of (half) the clock speed.
Suggested-by: Tomasz Figa <tomasz.figa@...il.com>
Signed-off-by: Łukasz Stelmach <l.stelmach@...sung.com>
---
drivers/spi/spi-s3c64xx.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
index 02de734b8ab1..89c162efe355 100644
--- a/drivers/spi/spi-s3c64xx.c
+++ b/drivers/spi/spi-s3c64xx.c
@@ -626,6 +626,7 @@ static int s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
ret = clk_set_rate(sdd->src_clk, sdd->cur_speed * 2);
if (ret)
return ret;
+ sdd->cur_speed = clk_get_rate(sdd->src_clk) / 2;
} else {
/* Configure Clock */
val = readl(regs + S3C64XX_SPI_CLK_CFG);
--
2.26.2
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