linux-kernel - Re: [PATCH] mtd: spi-nor: Fix 3-or-4 address byte mode logic

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Message-ID: <2c7b03eb-58fa-73af-93d7-669bad2e57ef@biot.com>
Date:   Sun, 4 Oct 2020 23:12:26 +0200
From:   Bert Vermeulen <bert@...t.com>
To:     David Laight <David.Laight@...LAB.COM>,
        Pratyush Yadav <p.yadav@...com>
Cc:     "tudor.ambarus@...rochip.com" <tudor.ambarus@...rochip.com>,
        "miquel.raynal@...tlin.com" <miquel.raynal@...tlin.com>,
        "richard@....at" <richard@....at>,
        "vigneshr@...com" <vigneshr@...com>,
        "linux-mtd@...ts.infradead.org" <linux-mtd@...ts.infradead.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] mtd: spi-nor: Fix 3-or-4 address byte mode logic

On 10/2/20 9:50 AM, David Laight wrote:
> From: Bert Vermeulen
>> The SoCs I'm dealing with have an SPI_ADDR_SEL pin, indicating whether it
>> should be in 3 or 4-byte mode. The vendor's hacked-up U-Boot sets the mode
>> accordingly, as does their BSP. It seems to me like a misfeature, and I want
>> to just ignore it and do reasonable JEDEC things, but I have the problem
>> that the flash chip can be in 4-byte mode by the time it gets to my spi-nor
>> driver.
> 
> If these are the devices I think they are, can't you read the
> non-volatile config word (bit 0) to find out whether the device
> expects a 3 or 4 byte address and how many 'idle' clocks there
> are before the read data?

I'm working with Realtek RTL838x/RTL839x SoCs. Reading it out is a
pretty convoluted procedure involving different I/O registers depending
on the SoC model.


-- 
Bert Vermeulen
bert@...t.com