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Message-ID: <20201006002404.GB6041@ranerica-svr.sc.intel.com>
Date:   Mon, 5 Oct 2020 17:24:04 -0700
From:   Ricardo Neri <ricardo.neri-calderon@...ux.intel.com>
To:     Borislav Petkov <bp@...en8.de>
Cc:     "Luck, Tony" <tony.luck@...el.com>,
        Thomas Gleixner <tglx@...utronix.de>, x86@...nel.org,
        Ingo Molnar <mingo@...nel.org>,
        Len Brown <len.brown@...el.com>,
        "Ravi V. Shankar" <ravi.v.shankar@...el.com>,
        linux-kernel@...r.kernel.org, Andy Lutomirski <luto@...nel.org>,
        "Peter Zijlstra (Intel)" <peterz@...radead.org>
Subject: Re: [PATCH 0/3] x86: Add initial support to discover Intel hybrid
 CPUs

On Sat, Oct 03, 2020 at 11:04:29AM +0200, Borislav Petkov wrote:
> On Fri, Oct 02, 2020 at 07:17:30PM -0700, Luck, Tony wrote:
> > On Sat, Oct 03, 2020 at 03:39:29AM +0200, Thomas Gleixner wrote:
> > > On Fri, Oct 02 2020 at 13:19, Ricardo Neri wrote:
> > > > Add support to discover and enumerate CPUs in Intel hybrid parts. A hybrid
> > > > part has CPUs with more than one type of micro-architecture. Thus, certain
> > > > features may only be present in a specific CPU type.
> > > >
> > > > It is useful to know the type of CPUs present in a system. For instance,
> > > > perf may need to handle CPUs differently depending on the type of micro-
> > > > architecture. Decoding machine check error logs may need the additional
> > > > micro-architecture type information, so include that in the log.
> > > 
> > > 'It is useful' as justification just makes me barf.
> > 
> > This isn't "hetero" ... all of the cores are architecturally the same.
> 
> But it says above "A hybrid part has CPUs with more than one type of
> micro-architecture."
> 
> So which is it?

Yes, even though they have different micro-architectures, all instructions and
features will be the same across CPUs.

> 
> > If CPUID says that some feature is supported, then it will be supported
> > on all of the cores.
> 
> Ok.
> 
> > There might be some model specific performance counter events that only
> > apply to some cores.
> 
> That sounds like the perf counter scheduling code would have to pay
> attention to what is supported. I think we have some functionality for
> that due to some AMD parts but I'd prefer if Peter comments here.
> 
> > Or a machine check error code that is logged in the model specific
> > MSCOD field of IA32_MCi_STATUS. But any and all code can run on any
> > core.
> 
> As long as that is consumed only by userspace I guess that's ok. The
> moment someone starts to want to differentiate on what kind of CPU
> kernel code runs and acts accordingly, then it becomes ugly so we better
> hash it out upfront.

We are not planning to implement changes as such.

Thanks and BR,
Ricardo

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