lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-Id: <160200545502.18883.1273632867328038422.b4-ty@arm.com>
Date:   Tue,  6 Oct 2020 18:31:15 +0100
From:   Catalin Marinas <catalin.marinas@....com>
To:     linux-arm-kernel@...ts.infradead.org,
        Jeremy Linton <jeremy.linton@....com>
Cc:     Will Deacon <will@...nel.org>, davem@...emloft.net,
        herbert@...dor.apana.org.au, linux-kernel@...r.kernel.org,
        dave.martin@....com, ardb@...nel.org, linux-crypto@...r.kernel.org,
        broonie@...nel.org
Subject: Re: [PATCH v3] crypto: arm64: Use x16 with indirect branch to bti_c

On Tue, 6 Oct 2020 11:33:26 -0500, Jeremy Linton wrote:
> The AES code uses a 'br x7' as part of a function called by
> a macro. That branch needs a bti_j as a target. This results
> in a panic as seen below. Using x16 (or x17) with an indirect
> branch keeps the target bti_c.
> 
>   Bad mode in Synchronous Abort handler detected on CPU1, code 0x34000003 -- BTI
>   CPU: 1 PID: 265 Comm: cryptomgr_test Not tainted 5.8.11-300.fc33.aarch64 #1
>   pstate: 20400c05 (nzCv daif +PAN -UAO BTYPE=j-)
>   pc : aesbs_encrypt8+0x0/0x5f0 [aes_neon_bs]
>   lr : aesbs_xts_encrypt+0x48/0xe0 [aes_neon_bs]
>   sp : ffff80001052b730
> 
> [...]

Applied to arm64 (for-next/fixes), thanks!

[1/1] crypto: arm64: Use x16 with indirect branch to bti_c
      https://git.kernel.org/arm64/c/39e4716caa59

-- 
Catalin

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ