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Message-ID: <20201006200316.2261245-2-lars.povlsen@microchip.com>
Date: Tue, 6 Oct 2020 22:03:14 +0200
From: Lars Povlsen <lars.povlsen@...rochip.com>
To: Sebastian Reichel <sre@...nel.org>,
Rob Herring <robh+dt@...nel.org>
CC: Lars Povlsen <lars.povlsen@...rochip.com>,
Alexandre Belloni <alexandre.belloni@...tlin.com>,
Microchip Linux Driver Support <UNGLinuxDriver@...rochip.com>,
<linux-pm@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>
Subject: [PATCH v2 1/3] dt-bindings: reset: ocelot: Add Sparx5 support
This adds the support for the Sparx5 SoC.
Signed-off-by: Lars Povlsen <lars.povlsen@...rochip.com>
---
.../devicetree/bindings/power/reset/ocelot-reset.txt | 7 +++++--
MAINTAINERS | 1 +
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt b/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt
index 1b4213eb3473..4d530d815484 100644
--- a/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt
+++ b/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt
@@ -1,10 +1,13 @@
Microsemi Ocelot reset controller
The DEVCPU_GCB:CHIP_REGS have a SOFT_RST register that can be used to reset the
-SoC MIPS core.
+SoC core.
+
+The reset registers are both present in the MSCC vcoreiii MIPS and
+microchip Sparx5 armv8 SoC's.
Required Properties:
- - compatible: "mscc,ocelot-chip-reset"
+ - compatible: "mscc,ocelot-chip-reset" or "microchip,sparx5-chip-reset"
Example:
reset@...0008 {
diff --git a/MAINTAINERS b/MAINTAINERS
index deaafb617361..cc70e3ab428b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -11516,6 +11516,7 @@ M: Microchip Linux Driver Support <UNGLinuxDriver@...rochip.com>
L: linux-mips@...r.kernel.org
S: Supported
F: Documentation/devicetree/bindings/mips/mscc.txt
+F: Documentation/devicetree/bindings/power/reset/ocelot-reset.txt
F: arch/mips/boot/dts/mscc/
F: arch/mips/configs/generic/board-ocelot.config
F: arch/mips/generic/board-ocelot.c
--
2.25.1
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