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Message-Id: <20201007101704.110101-1-tsbogend@alpha.franken.de> Date: Wed, 7 Oct 2020 12:17:04 +0200 From: Thomas Bogendoerfer <tsbogend@...ha.franken.de> To: linux-mips@...r.kernel.org, linux-kernel@...r.kernel.org Subject: [PATCH] MIPS: SGI-IP28: disable use of ll/sc in kernel SGI-IP28 systems only use broken R10k rev 2.5 CPUs, which could lock up, if ll/sc sequences are issued in certain order. Since those systems are all non-SMP, we can disable ll/sc usage in kernel. Signed-off-by: Thomas Bogendoerfer <tsbogend@...ha.franken.de> --- arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h index ba8b4e30b3e2..613bbc10c1f2 100644 --- a/arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h +++ b/arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h @@ -25,7 +25,7 @@ #define cpu_has_mcheck 0 #define cpu_has_ejtag 0 -#define cpu_has_llsc 1 +#define cpu_has_llsc 0 #define cpu_has_vtag_icache 0 #define cpu_has_dc_aliases 0 /* see probe_pcache() */ #define cpu_has_ic_fills_f_dc 0 -- 2.16.4
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