linux-kernel - [PATCH 1/5] memory: tegra: Correct la.reg address of seswr

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Message-Id: <20201008003746.25659-2-nicoleotsuka@gmail.com>
Date:   Wed,  7 Oct 2020 17:37:42 -0700
From:   Nicolin Chen <nicoleotsuka@...il.com>
To:     krzk@...nel.org, thierry.reding@...il.com, robh+dt@...nel.org
Cc:     jonathanh@...dia.com, linux-tegra@...r.kernel.org,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: [PATCH 1/5] memory: tegra: Correct la.reg address of seswr

According to Tegra X1 TRM, ALLOWANCE_SESWR is located in field
[23:16] of register at address 0x3e0 with a reset value of 0x80
at register 0x3e0, while bit-1 of register 0xb98 is for enable
bit of seswr. So this patch fixes it.

Signed-off-by: Nicolin Chen <nicoleotsuka@...il.com>
---
 drivers/memory/tegra/tegra210.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/memory/tegra/tegra210.c b/drivers/memory/tegra/tegra210.c
index 7fb8b5438bf4..088814279616 100644
--- a/drivers/memory/tegra/tegra210.c
+++ b/drivers/memory/tegra/tegra210.c
@@ -897,7 +897,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
 			.bit = 1,
 		},
 		.la = {
-			.reg = 0xb98,
+			.reg = 0x3e0,
 			.shift = 16,
 			.mask = 0xff,
 			.def = 0x80,
-- 
2.17.1