linux-kernel - [PATCH RFC v4 06/13] perf vendor events arm64: Add hip09 SMMUv3 PMCG events

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Thu, 8 Oct 2020 18:15:14 +0800
From:   John Garry <john.garry@...wei.com>
To:     <acme@...nel.org>, <will@...nel.org>, <mark.rutland@....com>,
        <jolsa@...hat.com>, <irogers@...gle.com>, <leo.yan@...aro.org>,
        <peterz@...radead.org>, <mingo@...hat.com>,
        <alexander.shishkin@...ux.intel.com>, <namhyung@...nel.org>,
        <mathieu.poirier@...aro.org>
CC:     <linuxarm@...wei.com>, <linux-kernel@...r.kernel.org>,
        <linux-arm-kernel@...ts.infradead.org>, <qiangqing.zhang@....com>,
        <zhangshaokun@...ilicon.com>, <james.clark@....com>,
        <linux-imx@....com>, John Garry <john.garry@...wei.com>
Subject: [PATCH RFC v4 06/13] perf vendor events arm64: Add hip09 SMMUv3 PMCG events

Add the SMMUv3 PMCG (Performance Monitor Event Group) events for hip09
platform.

This contains a mix of architected and IMP def events

Signed-off-by: John Garry <john.garry@...wei.com>
---
 .../hisilicon/hip09/sys/smmu-v3-pmcg.json     | 42 +++++++++++++++++++
 1 file changed, 42 insertions(+)
 create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/smmu-v3-pmcg.json

diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/smmu-v3-pmcg.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/smmu-v3-pmcg.json
new file mode 100644
index 000000000000..8abafbb2dcb4
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/smmu-v3-pmcg.json
@@ -0,0 +1,42 @@
+[
+   {
+	    "ArchStdEvent": "smmuv3_pmcg.CYCLES"
+	    "Compat": "0x00030736"
+   },
+   {
+	    "ArchStdEvent": "smmuv3_pmcg.TRANSACTION"
+	    "Compat": "0x00030736"
+   },
+   {
+	    "ArchStdEvent": "smmuv3_pmcg.TLB_MISS"
+	    "Compat": "0x00030736"
+   },
+   {
+	    "ArchStdEvent": "smmuv3_pmcg.CONFIG_CACHE_MISS"
+	    "Compat": "0x00030736"
+   },
+   {
+	    "ArchStdEvent": "smmuv3_pmcg.TRANS_TABLE_WALK_ACCESS"
+	    "Compat": "0x00030736"
+   },
+   {
+	    "ArchStdEvent": "smmuv3_pmcg.CONFIG_STRUCT_ACCESS"
+	    "Compat": "0x00030736"
+   },
+   {
+	    "ArchStdEvent": "smmuv3_pmcg.PCIE_ATS_TRANS_RQ"
+	    "Compat": "0x00030736"
+   },
+   {
+	    "ArchStdEvent": "smmuv3_pmcg.PCIE_ATS_TRANS_PASSED"
+	    "Compat": "0x00030736"
+   },
+   {
+	    "EventCode": "0x8a",
+	    "EventName": "smmuv3_pmcg.L1_TLB",
+	    "BriefDescription": "SMMUv3 PMCG L1 TABLE transation",
+	    "PublicDescription": "SMMUv3 PMCG L1 TABLE transation",
+	    "Unit": "smmuv3_pmcg",
+	    "Compat": "0x00030736"
+   },
+]
-- 
2.26.2