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Date: Thu, 8 Oct 2020 19:41:20 +0530
From: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
To: Rob Herring <robh@...nel.org>
Cc: rjw@...ysocki.net, viresh.kumar@...aro.org,
linux-pm@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, bjorn.andersson@...aro.org,
linux-arm-msm@...r.kernel.org
Subject: Re: [PATCH] dt-bindings: cpufreq: cpufreq-qcom-hw: Convert to YAML
bindings
On Wed, Oct 07, 2020 at 10:53:52AM -0500, Rob Herring wrote:
> On Tue, Oct 06, 2020 at 03:20:47PM +0530, Manivannan Sadhasivam wrote:
> > Convert Qualcomm cpufreq devicetree binding to YAML.
> >
> > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
> > ---
> > .../bindings/cpufreq/cpufreq-qcom-hw.txt | 172 --------------
> > .../bindings/cpufreq/cpufreq-qcom-hw.yaml | 212 ++++++++++++++++++
> > 2 files changed, 212 insertions(+), 172 deletions(-)
> > delete mode 100644 Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.txt
> > create mode 100644 Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml
>
> > diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml
> > new file mode 100644
> > index 000000000000..a11c69a29b5d
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml
> > @@ -0,0 +1,212 @@
[...]
> > +
> > + '#freq-domain-cells':
> > + const: 1
> > +
> > + qcom,freq-domain:
> > + $ref: /schemas/types.yaml#/definitions/phandle-array
> > + maxItems: 1
> > + description:
> > + Devices supporting freq-domain must set their "qcom,freq-domain"
> > + property with phandle to a cpufreq_hw followed by the Domain ID(0/1)
> > + in the CPU DT node.
>
> This doesn't belong here as it goes in cpu nodes. You're going to need
> to define a QCom cpu schema that defines this.
>
Okay. It was there in the original binding so I just kept it. Will remove it
in next iteration.
Thanks,
Mani
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - reg-names
> > + - clocks
> > + - clock-names
> > + - '#freq-domain-cells'
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/clock/qcom,gcc-sdm845.h>
> > + #include <dt-bindings/clock/qcom,rpmh.h>
> > +
> > + // Example 1: Dual-cluster, Quad-core per cluster. CPUs within a cluster
> > + // switch DCVS state together.
> > + cpus {
> > + #address-cells = <2>;
> > + #size-cells = <0>;
> > +
> > + CPU0: cpu@0 {
> > + device_type = "cpu";
> > + compatible = "qcom,kryo385";
> > + reg = <0x0 0x0>;
> > + enable-method = "psci";
> > + next-level-cache = <&L2_0>;
> > + qcom,freq-domain = <&cpufreq_hw 0>;
> > + L2_0: l2-cache {
> > + compatible = "cache";
> > + next-level-cache = <&L3_0>;
> > + L3_0: l3-cache {
> > + compatible = "cache";
> > + };
> > + };
> > + };
> > +
> > + CPU1: cpu@100 {
> > + device_type = "cpu";
> > + compatible = "qcom,kryo385";
> > + reg = <0x0 0x100>;
> > + enable-method = "psci";
> > + next-level-cache = <&L2_100>;
> > + qcom,freq-domain = <&cpufreq_hw 0>;
> > + L2_100: l2-cache {
> > + compatible = "cache";
> > + next-level-cache = <&L3_0>;
> > + };
> > + };
> > +
> > + CPU2: cpu@200 {
> > + device_type = "cpu";
> > + compatible = "qcom,kryo385";
> > + reg = <0x0 0x200>;
> > + enable-method = "psci";
> > + next-level-cache = <&L2_200>;
> > + qcom,freq-domain = <&cpufreq_hw 0>;
> > + L2_200: l2-cache {
> > + compatible = "cache";
> > + next-level-cache = <&L3_0>;
> > + };
> > + };
> > +
> > + CPU3: cpu@300 {
> > + device_type = "cpu";
> > + compatible = "qcom,kryo385";
> > + reg = <0x0 0x300>;
> > + enable-method = "psci";
> > + next-level-cache = <&L2_300>;
> > + qcom,freq-domain = <&cpufreq_hw 0>;
> > + L2_300: l2-cache {
> > + compatible = "cache";
> > + next-level-cache = <&L3_0>;
> > + };
> > + };
> > +
> > + CPU4: cpu@400 {
> > + device_type = "cpu";
> > + compatible = "qcom,kryo385";
> > + reg = <0x0 0x400>;
> > + enable-method = "psci";
> > + next-level-cache = <&L2_400>;
> > + qcom,freq-domain = <&cpufreq_hw 1>;
> > + L2_400: l2-cache {
> > + compatible = "cache";
> > + next-level-cache = <&L3_0>;
> > + };
> > + };
> > +
> > + CPU5: cpu@500 {
> > + device_type = "cpu";
> > + compatible = "qcom,kryo385";
> > + reg = <0x0 0x500>;
> > + enable-method = "psci";
> > + next-level-cache = <&L2_500>;
> > + qcom,freq-domain = <&cpufreq_hw 1>;
> > + L2_500: l2-cache {
> > + compatible = "cache";
> > + next-level-cache = <&L3_0>;
> > + };
> > + };
> > +
> > + CPU6: cpu@600 {
> > + device_type = "cpu";
> > + compatible = "qcom,kryo385";
> > + reg = <0x0 0x600>;
> > + enable-method = "psci";
> > + next-level-cache = <&L2_600>;
> > + qcom,freq-domain = <&cpufreq_hw 1>;
> > + L2_600: l2-cache {
> > + compatible = "cache";
> > + next-level-cache = <&L3_0>;
> > + };
> > + };
> > +
> > + CPU7: cpu@700 {
> > + device_type = "cpu";
> > + compatible = "qcom,kryo385";
> > + reg = <0x0 0x700>;
> > + enable-method = "psci";
> > + next-level-cache = <&L2_700>;
> > + qcom,freq-domain = <&cpufreq_hw 1>;
> > + L2_700: l2-cache {
> > + compatible = "cache";
> > + next-level-cache = <&L3_0>;
> > + };
> > + };
> > + };
> > +
> > + soc {
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > +
> > + cpufreq@...43000 {
> > + compatible = "qcom,cpufreq-hw";
> > + reg = <0x17d43000 0x1400>, <0x17d45800 0x1400>;
> > + reg-names = "freq-domain0", "freq-domain1";
> > +
> > + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
> > + clock-names = "xo", "alternate";
> > +
> > + #freq-domain-cells = <1>;
> > + };
> > + };
> > +...
> > --
> > 2.17.1
> >
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