lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:   Fri, 9 Oct 2020 13:56:25 +0530
From:   Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
To:     gokulsri@...eaurora.org
Cc:     sboyd@...nel.org, agross@...nel.org, bjorn.andersson@...aro.org,
        devicetree@...r.kernel.org, linux-arm-msm@...r.kernel.org,
        linux-kernel@...r.kernel.org, robh+dt@...nel.org,
        sricharan@...eaurora.org, kvalo@...eaurora.org
Subject: Re: [PATCH v3 3/3] arm64: dts: Enabled MHI device over PCIe

On Thu, Oct 08, 2020 at 11:03:42PM +0530, gokulsri@...eaurora.org wrote:
> On 2020-10-08 18:41, Manivannan Sadhasivam wrote:
> > Hi,
> > 
> > On Thu, Oct 08, 2020 at 06:02:24PM +0530, Gokul Sriram Palanisamy wrote:
> > > Enabled MHI device support over PCIe and added memory
> > > reservation required for MHI enabled QCN9000 PCIe card.
> > > 
> > > Signed-off-by: Gokul Sriram Palanisamy <gokulsri@...eaurora.org>
> > > ---
> > >  arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi | 47
> > > ++++++++++++++++++++++++++++++
> > >  1 file changed, 47 insertions(+)
> > > 
> > > diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi
> > > b/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi
> > > index 0827055..e5c1ec0 100644
> > > --- a/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi
> > > +++ b/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi

[...]

> > > +	pcie0_rp: pcie0_rp {
> > > +		reg = <0 0 0 0 0>;
> > > +
> > > +		status = "ok";
> > > +		mhi_0: qcom,mhi@0 {
> > 
> > MHI doesn't support devicetree as of now so how is this supposed to
> > work?
> > Have you tested this series with mainline?
> > 
> > Thanks,
> > Mani
> > 
> 
>  Hi Mani,
>  This node entries will be consumed by ath11k driver and is not supposed to
> be consumed by mhi driver.
>  And yes, it is tested on Mainline.
> 

Can you please point me to the relevant binding or the code which consumes this
change?

Also please explain what it does! For enabling MHI support over PCIe you don't
need this node at all. You just need to define the PCIe device ID in the ath11k
driver and that's it.

Adding Kalle to this thread...

Thanks,
Mani

>  Regards,
>  Gokul
> 
> > > +			reg = <0 0 0 0 0 >;
> > > +
> > > +			qrtr_instance_id = <0x20>;
> > > +			base-addr = <0x50f00000>;
> > > +			m3-dump-addr = <0x53c00000>;
> > > +			etr-addr = <0x53d00000>;
> > > +			qcom,caldb-addr = <0x53e00000>;
> > > +		};
> > > +	};
> > >  };
> > > 
> > >  &pcie1 {
> > >  	status = "ok";
> > >  	perst-gpio = <&tlmm 61 0x1>;
> > > +
> > > +	pcie1_rp: pcie1_rp {
> > > +		reg = <0 0 0 0 0>;
> > > +
> > > +		status = "ok";
> > > +		mhi_1: qcom,mhi@1 {
> > > +			reg = <0 0 0 0 0 >;
> > > +
> > > +			qrtr_instance_id = <0x21>;
> > > +			base-addr = <0x54600000>;
> > > +			m3-dump-addr = <0x57300000>;
> > > +			etr-addr = <0x57400000>;
> > > +			qcom,caldb-addr = <0x57500000>;
> > > +			};
> > > +		};
> > > +	};
> > >  };
> > > 
> > >  &qmp_pcie_phy0 {
> > > --
> > > 2.7.4
> > > 

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ