| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <20201012131739.1655-2-thunder.leizhen@huawei.com>
Date: Mon, 12 Oct 2020 21:17:29 +0800
From: Zhen Lei <thunder.leizhen@...wei.com>
To: Wei Xu <xuwei5@...ilicon.com>, Rob Herring <robh+dt@...nel.org>,
devicetree <devicetree@...r.kernel.org>,
linux-arm-kernel <linux-arm-kernel@...ts.infradead.org>,
linux-kernel <linux-kernel@...r.kernel.org>
CC: Zhen Lei <thunder.leizhen@...wei.com>
Subject: [PATCH 01/11] arm64: dts: hisilicon: normalize the node name of the ITS devices
Change the node name of the ITS devices to match
"^(msi-controller|gic-its|interrupt-controller)@[0-9a-f]+$". Although
"interrupt-controller" is allowed, but "msi-controller" is preferred.
Otherwise, "interrupt-controller@...00000: False schema does not allow"
will be reported by arm,gic-v3.yaml.
Signed-off-by: Zhen Lei <thunder.leizhen@...wei.com>
---
arch/arm64/boot/dts/hisilicon/hip05.dtsi | 8 ++++----
arch/arm64/boot/dts/hisilicon/hip06.dtsi | 2 +-
arch/arm64/boot/dts/hisilicon/hip07.dtsi | 16 ++++++++--------
3 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/arch/arm64/boot/dts/hisilicon/hip05.dtsi b/arch/arm64/boot/dts/hisilicon/hip05.dtsi
index bc49955360db754..f7e3a7af4634233 100644
--- a/arch/arm64/boot/dts/hisilicon/hip05.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hip05.dtsi
@@ -242,28 +242,28 @@
<0x0 0xfe020000 0 0x10000>; /* GICV */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
- its_peri: interrupt-controller@...00000 {
+ its_peri: msi-controller@...00000 {
compatible = "arm,gic-v3-its";
msi-controller;
#msi-cells = <1>;
reg = <0x0 0x8c000000 0x0 0x40000>;
};
- its_m3: interrupt-controller@...00000 {
+ its_m3: msi-controller@...00000 {
compatible = "arm,gic-v3-its";
msi-controller;
#msi-cells = <1>;
reg = <0x0 0xa3000000 0x0 0x40000>;
};
- its_pcie: interrupt-controller@...00000 {
+ its_pcie: msi-controller@...00000 {
compatible = "arm,gic-v3-its";
msi-controller;
#msi-cells = <1>;
reg = <0x0 0xb7000000 0x0 0x40000>;
};
- its_dsa: interrupt-controller@...00000 {
+ its_dsa: msi-controller@...00000 {
compatible = "arm,gic-v3-its";
msi-controller;
#msi-cells = <1>;
diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
index 50ceaa959bdc016..a2fba458e047fd7 100644
--- a/arch/arm64/boot/dts/hisilicon/hip06.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hip06.dtsi
@@ -242,7 +242,7 @@
<0x0 0xfe020000 0 0x10000>; /* GICV */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
- its_dsa: interrupt-controller@...00000 {
+ its_dsa: msi-controller@...00000 {
compatible = "arm,gic-v3-its";
msi-controller;
#msi-cells = <1>;
diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi b/arch/arm64/boot/dts/hisilicon/hip07.dtsi
index 4773a533fce589d..892691bb2adb446 100644
--- a/arch/arm64/boot/dts/hisilicon/hip07.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hip07.dtsi
@@ -924,56 +924,56 @@
<0x0 0xfe020000 0x0 0x10000>; /* GICV */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
- p0_its_peri_a: interrupt-controller@...00000 {
+ p0_its_peri_a: msi-controller@...00000 {
compatible = "arm,gic-v3-its";
msi-controller;
#msi-cells = <1>;
reg = <0x0 0x4c000000 0x0 0x40000>;
};
- p0_its_peri_b: interrupt-controller@...00000 {
+ p0_its_peri_b: msi-controller@...00000 {
compatible = "arm,gic-v3-its";
msi-controller;
#msi-cells = <1>;
reg = <0x0 0x6c000000 0x0 0x40000>;
};
- p0_its_dsa_a: interrupt-controller@...00000 {
+ p0_its_dsa_a: msi-controller@...00000 {
compatible = "arm,gic-v3-its";
msi-controller;
#msi-cells = <1>;
reg = <0x0 0xc6000000 0x0 0x40000>;
};
- p0_its_dsa_b: interrupt-controller@8,c6000000 {
+ p0_its_dsa_b: msi-controller@...000000 {
compatible = "arm,gic-v3-its";
msi-controller;
#msi-cells = <1>;
reg = <0x8 0xc6000000 0x0 0x40000>;
};
- p1_its_peri_a: interrupt-controller@400,4c000000 {
+ p1_its_peri_a: msi-controller@...4c000000 {
compatible = "arm,gic-v3-its";
msi-controller;
#msi-cells = <1>;
reg = <0x400 0x4c000000 0x0 0x40000>;
};
- p1_its_peri_b: interrupt-controller@400,6c000000 {
+ p1_its_peri_b: msi-controller@...6c000000 {
compatible = "arm,gic-v3-its";
msi-controller;
#msi-cells = <1>;
reg = <0x400 0x6c000000 0x0 0x40000>;
};
- p1_its_dsa_a: interrupt-controller@400,c6000000 {
+ p1_its_dsa_a: msi-controller@...c6000000 {
compatible = "arm,gic-v3-its";
msi-controller;
#msi-cells = <1>;
reg = <0x400 0xc6000000 0x0 0x40000>;
};
- p1_its_dsa_b: interrupt-controller@408,c6000000 {
+ p1_its_dsa_b: msi-controller@...c6000000 {
compatible = "arm,gic-v3-its";
msi-controller;
#msi-cells = <1>;
--
1.8.3
Powered by blists - more mailing lists