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Message-ID: <BYAPR11MB346391F798B3D13FD2863A18E0040@BYAPR11MB3463.namprd11.prod.outlook.com>
Date: Tue, 13 Oct 2020 23:00:05 +0000
From: "Brown, Len" <len.brown@...el.com>
To: Randy Dunlap <rdunlap@...radead.org>,
"Bae, Chang Seok" <chang.seok.bae@...el.com>,
"tglx@...utronix.de" <tglx@...utronix.de>,
"mingo@...nel.org" <mingo@...nel.org>, "bp@...e.de" <bp@...e.de>,
"luto@...nel.org" <luto@...nel.org>,
"x86@...nel.org" <x86@...nel.org>
CC: "Hansen, Dave" <dave.hansen@...el.com>,
"Liu, Jing2" <jing2.liu@...el.com>,
"Shankar, Ravi V" <ravi.v.shankar@...el.com>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"linux-doc@...r.kernel.org" <linux-doc@...r.kernel.org>
Subject: RE: [RFC PATCH 22/22] x86/fpu/xstate: Introduce boot-parameters for
control some state component support
> From: Randy Dunlap <rdunlap@...radead.org>
> What do these bitmasks look like? what do the bits mean?
> Where does a user find this info?
The XSAVE state component bitmaps are detailed in
the Intel Software Developer's Manual, volume 1, Chapter 13:
"Managing State using the XSAVE Feature Set".
http://intel.com/sdm
In the kernel source, they are enumerated in xstate.c
and you can observe them in dmesg:
[ 0.000000] x86/fpu: Supporting XSAVE feature 0x001: 'x87 floating point registers'
[ 0.000000] x86/fpu: Supporting XSAVE feature 0x002: 'SSE registers'
[ 0.000000] x86/fpu: Supporting XSAVE feature 0x004: 'AVX registers'
[ 0.000000] x86/fpu: Supporting XSAVE feature 0x008: 'MPX bounds registers'
[ 0.000000] x86/fpu: Supporting XSAVE feature 0x010: 'MPX CSR'
Thanks,
-Len
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