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Message-ID: <c3baadae-8e20-86a6-44f5-4571a8d3035e@arm.com>
Date: Tue, 13 Oct 2020 14:42:38 +0100
From: Robin Murphy <robin.murphy@....com>
To: Christoph Hellwig <hch@...radead.org>,
Jonathan Marek <jonathan@...ek.ca>
Cc: freedreno@...ts.freedesktop.org, Rob Clark <robdclark@...il.com>,
Sean Paul <sean@...rly.run>, David Airlie <airlied@...ux.ie>,
Daniel Vetter <daniel@...ll.ch>,
"open list:DRM DRIVER FOR MSM ADRENO GPU"
<linux-arm-msm@...r.kernel.org>,
"open list:DRM DRIVER FOR MSM ADRENO GPU"
<dri-devel@...ts.freedesktop.org>,
open list <linux-kernel@...r.kernel.org>,
iommu@...ts.linux-foundation.org, Joerg Roedel <joro@...tes.org>
Subject: Re: [PATCH 2/3] drm/msm: add DRM_MSM_GEM_SYNC_CACHE for non-coherent
cache maintenance
On 2020-10-07 07:25, Christoph Hellwig wrote:
> On Tue, Oct 06, 2020 at 09:19:32AM -0400, Jonathan Marek wrote:
>> One example why drm/msm can't use DMA API is multiple page table support
>> (that is landing in 5.10), which is something that definitely couldn't work
>> with DMA API.
>>
>> Another one is being able to choose the address for mappings, which AFAIK
>> DMA API can't do (somewhat related to this: qcom hardware often has ranges
>> of allowed addresses, which the dma_mask mechanism fails to represent, what
>> I see is drivers using dma_mask as a "maximum address", and since addresses
>> are allocated from the top it generally works)
>
> That sounds like a good enough rason to use the IOMMU API. I just
> wanted to make sure this really makes sense.
I still think this situation would be best handled with a variant of
dma_ops_bypass that also guarantees to bypass SWIOTLB, and can be set
automatically when attaching to an unmanaged IOMMU domain. That way the
device driver can make DMA API calls in the appropriate places that do
the right thing either way, and only needs logic to decide whether to
use the returned DMA addresses directly or ignore them if it knows
they're overridden by its own IOMMU mapping.
Robin.
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