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Message-ID: <de47984b-9a69-733c-3bd1-7b24ceb9b7f0@linux.intel.com>
Date: Tue, 13 Oct 2020 10:57:41 -0400
From: "Liang, Kan" <kan.liang@...ux.intel.com>
To: Will Deacon <will@...nel.org>,
Michael Ellerman <mpe@...erman.id.au>,
Peter Zijlstra <peterz@...radead.org>
Cc: mingo@...hat.com, acme@...nel.org, linux-kernel@...r.kernel.org,
mark.rutland@....com, alexander.shishkin@...ux.intel.com,
jolsa@...hat.com, eranian@...gle.com, ak@...ux.intel.com,
dave.hansen@...el.com, kirill.shutemov@...ux.intel.com,
benh@...nel.crashing.org, paulus@...ba.org,
David Miller <davem@...emloft.net>
Subject: Re: [PATCH V9 1/4] perf/core: Add PERF_SAMPLE_DATA_PAGE_SIZE
On 10/12/2020 4:48 AM, Will Deacon wrote:
> On Sat, Oct 10, 2020 at 12:28:39AM +1100, Michael Ellerman wrote:
>> Peter Zijlstra <peterz@...radead.org> writes:
>>> Patch 4 makes it all far worse by exposing it to pretty much everybody.
>>>
>>> Now, I think we can fix at least the user mappings with the below delta,
>>> but if archs are using non-page-table MMU sizes we'll need arch helpers.
>>>
>>> ARM64 is in that last boat.
>>
>> I think we probably need it to be weak so we can provide our own
>> version.
>
> I guess the same thing applies to us, but I can't really tell how accurate
> this stuff needs to be for userspace. If it's trying to use the page-table
> configuration to infer properties of the TLB, that's never going to be
> reliable because the TLB can choose both to split and coalesce entries
> as long as software can't tell.
>
Hi Peter,
It looks like everybody wants a __weak function. If so, I guess we
should drop the generic code in this patch. For X86, we have existing
functions to retrieve the page level and the page size. I think we don't
need the generic code either.
https://lkml.kernel.org/r/1549648509-12704-2-git-send-email-kan.liang@linux.intel.com/
Should I send a V10 patch to drop the generic code and implement an X86
specific perf_get_page_size()? Will, Michael, and others can implement
their version later separately.
Thanks,
Kan
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