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Message-ID: <160264369288.310579.9004484766033537806@swboyd.mtv.corp.google.com>
Date:   Tue, 13 Oct 2020 19:48:12 -0700
From:   Stephen Boyd <sboyd@...nel.org>
To:     Qiang Zhao <qiang.zhao@....com>, mturquette@...libre.com,
        robh+dt@...nel.org, shawnguo@...nel.org
Cc:     andy.tang@....com, linux-kernel@...r.kernel.org,
        devicetree@...r.kernel.org, linux-clk@...r.kernel.org,
        Zhao Qiang <qiang.zhao@....com>
Subject: Re: [PATCH 1/2] clk: qoriq: modify MAX_PLL_DIV to 32

Quoting Qiang Zhao (2020-09-15 20:03:10)
> From: Zhao Qiang <qiang.zhao@....com>
> 
> On LS2088A, Watchdog need clk divided by 32,
> so modify MAX_PLL_DIV to 32
> 
> Signed-off-by: Zhao Qiang <qiang.zhao@....com>
> ---

Applied to clk-next

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