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Message-ID: <160264478758.310579.1897903039659830056@swboyd.mtv.corp.google.com>
Date: Tue, 13 Oct 2020 20:06:27 -0700
From: Stephen Boyd <sboyd@...nel.org>
To: Michael Turquette <mturquette@...libre.com>,
Paul Cercueil <paul@...pouillou.net>
Cc: od@...c.me, linux-clk@...r.kernel.org,
linux-kernel@...r.kernel.org, Paul Cercueil <paul@...pouillou.net>
Subject: Re: [PATCH 3/5] clk: ingenic: Don't use CLK_SET_RATE_GATE for PLL
Quoting Paul Cercueil (2020-09-02 18:50:46)
> CLK_SET_RATE_GATE means that the clock must be gated when being
> reclocked. This is not the case for the PLLs in Ingenic SoCs.
>
> Signed-off-by: Paul Cercueil <paul@...pouillou.net>
> ---
Applied to clk-next
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