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Message-Id: <1602645639-12854-1-git-send-email-dphadke@linux.microsoft.com>
Date: Tue, 13 Oct 2020 20:20:39 -0700
From: Dhananjay Phadke <dphadke@...ux.microsoft.com>
To: rayagonda.kokatanur@...adcom.com
Cc: andriy.shevchenko@...ux.intel.com,
bcm-kernel-feedback-list@...adcom.com, brendanhiggins@...gle.com,
dphadke@...ux.microsoft.com, f.fainelli@...il.com,
linux-arm-kernel@...ts.infradead.org, linux-i2c@...r.kernel.org,
linux-kernel@...r.kernel.org, lori.hikichi@...adcom.com,
rjui@...adcom.com, sbranden@...adcom.com, wsa@...nel.org
Subject: [PATCH v1 5/6] i2c: iproc: handle master read request
On Sun, 11 Oct 2020 23:52:53 +0530, Rayagonda Kokatanur wrote:
> --- a/drivers/i2c/busses/i2c-bcm-iproc.c
> +++ b/drivers/i2c/busses/i2c-bcm-iproc.c
>
> - } else if (status & BIT(IS_S_RD_EVENT_SHIFT)) {
> - /* Start of SMBUS for Master Read */
> + I2C_SLAVE_WRITE_REQUESTED, &rx_data);
> + iproc_i2c->rx_start_rcvd = true;
> + iproc_i2c->slave_read_complete = false;
> + } else if (rx_status == I2C_SLAVE_RX_DATA &&
> + iproc_i2c->rx_start_rcvd) {
> + /* Middle of SMBUS Master write */
> i2c_slave_event(iproc_i2c->slave,
> - I2C_SLAVE_READ_REQUESTED, &value);
> - iproc_i2c_wr_reg(iproc_i2c, S_TX_OFFSET, value);
> + I2C_SLAVE_WRITE_RECEIVED, &rx_data);
> + } else if (rx_status == I2C_SLAVE_RX_END &&
> + iproc_i2c->rx_start_rcvd) {
> + /* End of SMBUS Master write */
> + if (iproc_i2c->slave_rx_only)
> + i2c_slave_event(iproc_i2c->slave,
> + I2C_SLAVE_WRITE_RECEIVED,
> + &rx_data);
> +
> + i2c_slave_event(iproc_i2c->slave, I2C_SLAVE_STOP,
> + &rx_data);
> + } else if (rx_status == I2C_SLAVE_RX_FIFO_EMPTY) {
> + iproc_i2c->rx_start_rcvd = false;
> + iproc_i2c->slave_read_complete = true;
> + break;
> + }
>
> - val = BIT(S_CMD_START_BUSY_SHIFT);
> - iproc_i2c_wr_reg(iproc_i2c, S_CMD_OFFSET, val);
> + rx_bytes++;
rx_bytes should be incremented only along with I2C_SLAVE_WRITE_RECEIVED event?
>
> +static bool bcm_iproc_i2c_slave_isr(struct bcm_iproc_i2c_dev *iproc_i2c,
> + u32 status)
> +{
> + u32 val;
> + u8 value;
> +
> + /*
> + * Slave events in case of master-write, master-write-read and,
> + * master-read
> + *
> + * Master-write : only IS_S_RX_EVENT_SHIFT event
> + * Master-write-read: both IS_S_RX_EVENT_SHIFT and IS_S_RD_EVENT_SHIFT
> + * events
> + * Master-read : both IS_S_RX_EVENT_SHIFT and IS_S_RD_EVENT_SHIFT
> + * events or only IS_S_RD_EVENT_SHIFT
> + */
> + if (status & BIT(IS_S_RX_EVENT_SHIFT) ||
> + status & BIT(IS_S_RD_EVENT_SHIFT)) {
> + /* disable slave interrupts */
> + val = iproc_i2c_rd_reg(iproc_i2c, IE_OFFSET);
> + val &= ~iproc_i2c->slave_int_mask;
> + iproc_i2c_wr_reg(iproc_i2c, IE_OFFSET, val);
> +
> + if (status & BIT(IS_S_RD_EVENT_SHIFT))
> + /* Master-write-read request */
> + iproc_i2c->slave_rx_only = false;
> + else
> + /* Master-write request only */
> + iproc_i2c->slave_rx_only = true;
> +
> + /* schedule tasklet to read data later */
> + tasklet_schedule(&iproc_i2c->slave_rx_tasklet);
> +
> + /* clear only IS_S_RX_EVENT_SHIFT interrupt */
> + iproc_i2c_wr_reg(iproc_i2c, IS_OFFSET,
> + BIT(IS_S_RX_EVENT_SHIFT));
>
Both tasklet and isr are writing to status (IS_OFFSET) reg.
The tasklet seems to be batching up rx fifo reads because of time-sensitive
Master-write-read transaction? Linux I2C framework is byte interface anyway.
Can the need to batch reads be avoided by setting slave rx threshold for
interrupt (S_FIFO_RX_THLD) to 1-byte?
Also, wouldn't tasklets be susceptible to other interrupts? If fifo reads
have to be batched up, can it be changed to threaded irq?
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