linux-kernel - Re: [PATCH RFC v4 06/13] perf vendor events arm64: Add hip09 SMMUv3 PMCG events

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Date:   Thu, 15 Oct 2020 08:47:45 +0100
From:   John Garry <john.garry@...wei.com>
To:     Robin Murphy <robin.murphy@....com>, <acme@...nel.org>,
        <will@...nel.org>, <mark.rutland@....com>, <jolsa@...hat.com>,
        <irogers@...gle.com>, <leo.yan@...aro.org>, <peterz@...radead.org>,
        <mingo@...hat.com>, <alexander.shishkin@...ux.intel.com>,
        <namhyung@...nel.org>, <mathieu.poirier@...aro.org>
CC:     <linux-kernel@...r.kernel.org>, <qiangqing.zhang@....com>,
        <linuxarm@...wei.com>, <zhangshaokun@...ilicon.com>,
        <james.clark@....com>, <linux-arm-kernel@...ts.infradead.org>,
        <linux-imx@....com>
Subject: Re: [PATCH RFC v4 06/13] perf vendor events arm64: Add hip09 SMMUv3
 PMCG events

On 14/10/2020 19:06, Robin Murphy wrote:
>>
>> +        "EventCode": "0x8a",
>> +        "EventName": "smmuv3_pmcg.L1_TLB",
>> +        "BriefDescription": "SMMUv3 PMCG L1 TABLE transation",
>> +        "PublicDescription": "SMMUv3 PMCG L1 TABLE transation",
> 
> Those typos are either missing "c"s or "l"s, but with SMMU it's never 
> clear which ;)

Ha, I think either could work in this case.

The actual electronic translation I got is "command received by the L1 
TLB", so I'll stick with that until someone here wants to expand on that.

Cheers