linux-kernel - Re: [PATCH] clk: imx8mq: Fix usdhc parents order

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Message-ID: <CAOMZO5DxZN_cniuy2xhYGWAr3rjNBZNJAJvYcH+KNBa+S7S2mg@mail.gmail.com>
Date:   Thu, 15 Oct 2020 08:22:28 -0300
From:   Fabio Estevam <festevam@...il.com>
To:     Abel Vesa <abel.vesa@....com>
Cc:     Mike Turquette <mturquette@...libre.com>,
        Stephen Boyd <sboyd@...nel.org>,
        Shawn Guo <shawnguo@...nel.org>,
        Sascha Hauer <kernel@...gutronix.de>,
        Fabio Estevam <fabio.estevam@....com>,
        Peng Fan <peng.fan@....com>,
        Dong Aisheng <aisheng.dong@....com>,
        Anson Huang <anson.huang@....com>,
        Lucas Stach <l.stach@...gutronix.de>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        linux-clk <linux-clk@...r.kernel.org>,
        "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" 
        <linux-arm-kernel@...ts.infradead.org>,
        NXP Linux Team <linux-imx@....com>
Subject: Re: [PATCH] clk: imx8mq: Fix usdhc parents order

Hi Abel,

On Thu, Oct 15, 2020 at 6:26 AM Abel Vesa <abel.vesa@....com> wrote:
>
> According to the latest RM (see Table 5-1. Clock Root Table),
> both usdhc root clocks have the parent order as follows:
>
> 000 - 25M_REF_CLK
> 001 - SYSTEM_PLL1_DIV2
> 010 - SYSTEM_PLL1_CLK
> 011 - SYSTEM_PLL2_DIV2
> 100 - SYSTEM_PLL3_CLK
> 101 - SYSTEM_PLL1_DIV3
> 110 - AUDIO_PLL2_CLK
> 111 - SYSTEM_PLL1_DIV8
>
> So the audio_pll2_out and sys3_pll_out have to be swapped.
>
> Fixes: b80522040cd3 ("clk: imx: Add clock driver for i.MX8MQ CCM")
> Signed-off-by: Abel Vesa <abel.vesa@....com>
> Reported-by: Cosmin Stefan Stoica <cosmin.stoica@....com>

Thanks for the fix:

Reviewed-by: Fabio Estevam <festevam@...il.com>