linux-kernel - [PATCH 1/4] clk: renesas: rcar-gen3: Add support to pass custom RPCSRC div table

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Date:   Fri, 16 Oct 2020 13:17:06 +0100
From:   Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
To:     Geert Uytterhoeven <geert+renesas@...der.be>,
        Michael Turquette <mturquette@...libre.com>,
        Stephen Boyd <sboyd@...nel.org>,
        linux-renesas-soc@...r.kernel.org, linux-clk@...r.kernel.org
Cc:     linux-kernel@...r.kernel.org,
        Biju Das <biju.das.jz@...renesas.com>,
        Prabhakar <prabhakar.csengg@...il.com>,
        Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: [PATCH 1/4] clk: renesas: rcar-gen3: Add support to pass custom RPCSRC div table

RPCSRC div table is SoC specific and is not common for all R-Car Gen3
devices, with the current implementation in rcar-gen3-cpg not all the
SoC's are covered.

To handle such case introduce a new member cpg_rpcsrc_div_table in
priv structure so that we pass SoC specific div table for RPCSRC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Reviewed-by: Biju Das <biju.das.jz@...renesas.com>
---
 drivers/clk/renesas/rcar-gen3-cpg.c    | 2 ++
 drivers/clk/renesas/renesas-cpg-mssr.h | 6 ++++++
 2 files changed, 8 insertions(+)

diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c
index 488f8b3980c5..cdfcd108d1a3 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.c
+++ b/drivers/clk/renesas/rcar-gen3-cpg.c
@@ -693,6 +693,8 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
 		return clk_register_divider_table(NULL, core->name,
 						  __clk_get_name(parent), 0,
 						  base + CPG_RPCCKCR, 3, 2, 0,
+						  info->cpg_rpcsrc_div_table ?
+						  info->cpg_rpcsrc_div_table :
 						  cpg_rpcsrc_div_table,
 						  &cpg_lock);
 
diff --git a/drivers/clk/renesas/renesas-cpg-mssr.h b/drivers/clk/renesas/renesas-cpg-mssr.h
index f369b06c903b..3b0a70c59e04 100644
--- a/drivers/clk/renesas/renesas-cpg-mssr.h
+++ b/drivers/clk/renesas/renesas-cpg-mssr.h
@@ -8,6 +8,8 @@
 #ifndef __CLK_RENESAS_CPG_MSSR_H__
 #define __CLK_RENESAS_CPG_MSSR_H__
 
+#include <linux/clk-provider.h>
+
     /*
      * Definitions of CPG Core Clocks
      *
@@ -116,6 +118,8 @@ enum clk_reg_layout {
      *                Management, in addition to Module Clocks
      * @num_core_pm_clks: Number of entries in core_pm_clks[]
      *
+     * @cpg_rpcsrc_div_table: DIV table for RPCSRC
+     *
      * @init: Optional callback to perform SoC-specific initialization
      * @cpg_clk_register: Optional callback to handle special Core Clock types
      */
@@ -147,6 +151,8 @@ struct cpg_mssr_info {
 	const unsigned int *core_pm_clks;
 	unsigned int num_core_pm_clks;
 
+	const struct clk_div_table *cpg_rpcsrc_div_table;
+
 	/* Callbacks */
 	int (*init)(struct device *dev);
 	struct clk *(*cpg_clk_register)(struct device *dev,
-- 
2.17.1