lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:   Sun, 18 Oct 2020 00:51:23 +0530
From:   Taniya Das <tdas@...eaurora.org>
To:     Stephen Boyd <sboyd@...nel.org>,
        Michael Turquette <mturquette@...libre.com>
Cc:     linux-kernel@...r.kernel.org, linux-clk@...r.kernel.org,
        Douglas Anderson <dianders@...omium.org>,
        Rajendra Nayak <rnayak@...eaurora.org>
Subject: Re: [PATCH] clk: qcom: gdsc: Keep RETAIN_FF bit set if gdsc is
 already on

Reviewed-by: Taniya Das <tdas@...eaurora.org>

On 10/17/2020 7:31 AM, Stephen Boyd wrote:
> If the GDSC is enabled out of boot but doesn't have the retain ff bit
> set we will get confusing results where the registers that are powered
> by the GDSC lose their contents on the first power off of the GDSC but
> thereafter they retain their contents. This is because gdsc_init() fails
> to make sure the RETAIN_FF bit is set when it probes the GDSC the first
> time and thus powering off the GDSC causes the register contents to be
> reset. We do set the RETAIN_FF bit the next time we power on the GDSC,
> see gdsc_enable(), so that subsequent GDSC power off's don't lose
> register contents state.
> 
> Forcibly set the bit at device probe time so that the kernel's assumed
> view of the GDSC is consistent with the state of the hardware. This
> fixes a problem where the audio PLL doesn't work on sc7180 when the
> bootloader leaves the lpass_core_hm GDSC enabled at boot (e.g. to make a
> noise) but critically doesn't set the RETAIN_FF bit.
> 
> Cc: Douglas Anderson <dianders@...omium.org>
> Cc: Taniya Das <tdas@...eaurora.org>
> Cc: Rajendra Nayak <rnayak@...eaurora.org>
> Fixes: 173722995cdb ("clk: qcom: gdsc: Add support to enable retention of GSDCR")
> Signed-off-by: Stephen Boyd <sboyd@...nel.org>
> ---
>   drivers/clk/qcom/gdsc.c | 8 ++++++++
>   1 file changed, 8 insertions(+)
> 
> diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c
> index bfc4ac02f9ea..af26e0695b86 100644
> --- a/drivers/clk/qcom/gdsc.c
> +++ b/drivers/clk/qcom/gdsc.c
> @@ -358,6 +358,14 @@ static int gdsc_init(struct gdsc *sc)
>   	if ((sc->flags & VOTABLE) && on)
>   		gdsc_enable(&sc->pd);
>   
> +	/*
> +	 * Make sure the retain bit is set if the GDSC is already on, otherwise
> +	 * we end up turning off the GDSC and destroying all the register
> +	 * contents that we thought we were saving.
> +	 */
> +	if ((sc->flags & RETAIN_FF_ENABLE) && on)
> +		gdsc_retain_ff_on(sc);
> +
>   	/* If ALWAYS_ON GDSCs are not ON, turn them ON */
>   	if (sc->flags & ALWAYS_ON) {
>   		if (!on)
> 
> base-commit: 9ff9b0d392ea08090cd1780fb196f36dbb586529
> 

-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation.

--

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ