linux-kernel - Re: [PATCH 2/2] net: dsa: mv88e6xxx: Support serdes ports on MV88E6097

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Sun, 18 Oct 2020 20:09:46 +0000
From:   Chris Packham <Chris.Packham@...iedtelesis.co.nz>
To:     Andrew Lunn <andrew@...n.ch>
CC:     "vivien.didelot@...il.com" <vivien.didelot@...il.com>,
        "f.fainelli@...il.com" <f.fainelli@...il.com>,
        "olteanv@...il.com" <olteanv@...il.com>,
        "davem@...emloft.net" <davem@...emloft.net>,
        "kuba@...nel.org" <kuba@...nel.org>,
        "linux@...linux.org.uk" <linux@...linux.org.uk>,
        "netdev@...r.kernel.org" <netdev@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 2/2] net: dsa: mv88e6xxx: Support serdes ports on
 MV88E6097


On 19/10/20 5:16 am, Andrew Lunn wrote:
> On Tue, Oct 13, 2020 at 03:18:58PM +1300, Chris Packham wrote:
>> Implement serdes_power, serdes_get_lane and serdes_pcs_get_state ops for
>> the MV88E6097 so that ports 8 & 9 can be supported as serdes ports and
>> directly connected to other network interfaces or to SFPs without a PHY.
>>
>> Signed-off-by: Chris Packham <chris.packham@...iedtelesis.co.nz>
>> ---
>>
>> This should be usable for all variants of the 88E6185 that have
>> tri-speed capable ports (which is why I used the mv88e6185 prefix
>> instead of mv88e6097). But my hardware only has a 88e6097 so I've only
>> connected up the ops for that chip.
>>
>>   drivers/net/dsa/mv88e6xxx/chip.c | 61 ++++++++++++++++++++++++++++++++
>>   1 file changed, 61 insertions(+)
>>
>> diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c
>> index 1ef392ee52c5..1c6cd5c43eb1 100644
>> --- a/drivers/net/dsa/mv88e6xxx/chip.c
>> +++ b/drivers/net/dsa/mv88e6xxx/chip.c
>> @@ -3436,6 +3436,64 @@ static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
>>   	return err;
>>   }
>>   
>> +static int mv88e6185_serdes_power(struct mv88e6xxx_chip *chip, int port, u8 lane,
>> +				  bool up)
>> +{
>> +	/* The serdes power can't be controlled on this switch chip but we need
>> +	 * to supply this function to avoid returning -EOPNOTSUPP in
>> +	 * mv88e6xxx_serdes_power_up/mv88e6xxx_serdes_power_down
>> +	 */
> Hi Chris
>
> How about bit 11 of the control register 0? This looks a lot like a
> BMCR, and BMCR_PDOWN.
>
> This is what mv88e6352_serdes_power() does. You might be able to even
> re-use it, if you can make the lane numbers work.

I assume you're talking about the PHY Control Register 0 bit 11. If so 
that's for the internal PHYs on ports 0-7. Ports 8, 9 and 10 don't have 
PHYs.