linux-kernel - Re: [PATCH 2/5] pwm: pwm-mediatek: always use bus clock

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Date:   Mon, 19 Oct 2020 16:27:38 +0200
From:   Matthias Brugger <matthias.bgg@...il.com>
To:     Fabien Parent <fparent@...libre.com>,
        linux-mediatek@...ts.infradead.org,
        linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
        devicetree@...r.kernel.org, linux-pwm@...r.kernel.org
Cc:     robh+dt@...nel.org, lee.jones@...aro.org,
        u.kleine-koenig@...gutronix.de, thierry.reding@...il.com
Subject: Re: [PATCH 2/5] pwm: pwm-mediatek: always use bus clock



On 19/10/2020 16:07, Fabien Parent wrote:
> The MediaTek PWM IP can sometimes use the 26MHz source clock to generate
> the PWM signal, but the driver currently assumes that we always use
> the PWM bus clock to generate the PWM signal.
> 
> This commit modifies the PWM driver in order to force the PWM IP to
> always use the bus clock as source clock.
> 
> I do not have the datasheet of all the MediaTek SoC, so I don't know
> if the register to choose the source clk is present in all the SoCs
> or only in subset. As a consequence I made this change optional by
> using a platform data paremeter to says whether this register is
> supported or not. On all the SoC I don't have the datasheet
> (MT2712, MT7622, MT7623, MT7628, MT7629) I kept the behavior
> to be the same as before this change.
> 
> Signed-off-by: Fabien Parent <fparent@...libre.com>

Reviewed-by: Matthias Brugger <matthias.bgg@...il.com>

> ---
>   drivers/pwm/pwm-mediatek.c | 12 ++++++++++++
>   1 file changed, 12 insertions(+)
> 
> diff --git a/drivers/pwm/pwm-mediatek.c b/drivers/pwm/pwm-mediatek.c
> index ab001ce55178..108881619aea 100644
> --- a/drivers/pwm/pwm-mediatek.c
> +++ b/drivers/pwm/pwm-mediatek.c
> @@ -30,12 +30,14 @@
>   #define PWM45DWIDTH_FIXUP	0x30
>   #define PWMTHRES		0x30
>   #define PWM45THRES_FIXUP	0x34
> +#define PWM_CK_26M_SEL		0x210
>   
>   #define PWM_CLK_DIV_MAX		7
>   
>   struct pwm_mediatek_of_data {
>   	unsigned int num_pwms;
>   	bool pwm45_fixup;
> +	bool has_ck_26m_sel;
>   };
>   
>   /**
> @@ -132,6 +134,10 @@ static int pwm_mediatek_config(struct pwm_chip *chip, struct pwm_device *pwm,
>   	if (ret < 0)
>   		return ret;
>   
> +	/* Make sure we use the bus clock and not the 26MHz clock */
> +	if (pc->soc->has_ck_26m_sel)
> +		writel(0, pc->regs + PWM_CK_26M_SEL);
> +
>   	/* Using resolution in picosecond gets accuracy higher */
>   	resolution = (u64)NSEC_PER_SEC * 1000;
>   	do_div(resolution, clk_get_rate(pc->clk_pwms[pwm->hwpwm]));
> @@ -281,31 +287,37 @@ static int pwm_mediatek_remove(struct platform_device *pdev)
>   static const struct pwm_mediatek_of_data mt2712_pwm_data = {
>   	.num_pwms = 8,
>   	.pwm45_fixup = false,
> +	.has_ck_26m_sel = false,
>   };
>   
>   static const struct pwm_mediatek_of_data mt7622_pwm_data = {
>   	.num_pwms = 6,
>   	.pwm45_fixup = false,
> +	.has_ck_26m_sel = false,
>   };
>   
>   static const struct pwm_mediatek_of_data mt7623_pwm_data = {
>   	.num_pwms = 5,
>   	.pwm45_fixup = true,
> +	.has_ck_26m_sel = false,
>   };
>   
>   static const struct pwm_mediatek_of_data mt7628_pwm_data = {
>   	.num_pwms = 4,
>   	.pwm45_fixup = true,
> +	.has_ck_26m_sel = false,
>   };
>   
>   static const struct pwm_mediatek_of_data mt7629_pwm_data = {
>   	.num_pwms = 1,
>   	.pwm45_fixup = false,
> +	.has_ck_26m_sel = false,
>   };
>   
>   static const struct pwm_mediatek_of_data mt8516_pwm_data = {
>   	.num_pwms = 5,
>   	.pwm45_fixup = false,
> +	.has_ck_26m_sel = true,
>   };
>   
>   static const struct of_device_id pwm_mediatek_of_match[] = {
>