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Message-ID: <2bde9a4d-25bc-0ac7-d6e4-762667cc4fd2@arm.com>
Date: Mon, 19 Oct 2020 19:50:10 +0100
From: Robin Murphy <robin.murphy@....com>
To: Bjorn Andersson <bjorn.andersson@...aro.org>,
Will Deacon <will@...nel.org>, Joerg Roedel <joro@...tes.org>,
Sai Prakash Ranjan <saiprakash.ranjan@...eaurora.org>,
Jordan Crouse <jcrouse@...eaurora.org>,
Thierry Reding <treding@...dia.com>,
Rob Clark <robdclark@...omium.org>
Cc: linux-arm-kernel@...ts.infradead.org,
iommu@...ts.linux-foundation.org, linux-kernel@...r.kernel.org,
linux-arm-msm@...r.kernel.org
Subject: Re: [PATCH v5 2/3] iommu/arm-smmu-qcom: Read back stream mappings
On 2020-10-19 19:23, Bjorn Andersson wrote:
> The Qualcomm boot loader configures stream mapping for the peripherals
> that it accesses and in particular it sets up the stream mapping for the
> display controller to be allowed to scan out a splash screen or EFI
> framebuffer.
>
> Read back the stream mappings during initialization and make the
> arm-smmu driver maintain the streams in bypass mode.
Acked-by: Robin Murphy <robin.murphy@....com>
> Signed-off-by: Bjorn Andersson <bjorn.andersson@...aro.org>
> ---
>
> Changes since v4:
> - Don't increment s2cr[i]->count, as this is not actually needed to survive
> probe deferral
>
> drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 23 ++++++++++++++++++++++
> 1 file changed, 23 insertions(+)
>
> diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
> index be4318044f96..48627fcf6bed 100644
> --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
> +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
> @@ -23,6 +23,28 @@ static const struct of_device_id qcom_smmu_client_of_match[] __maybe_unused = {
> { }
> };
>
> +static int qcom_smmu_cfg_probe(struct arm_smmu_device *smmu)
> +{
> + u32 smr;
> + int i;
> +
> + for (i = 0; i < smmu->num_mapping_groups; i++) {
> + smr = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_SMR(i));
> +
> + if (FIELD_GET(ARM_SMMU_SMR_VALID, smr)) {
> + smmu->smrs[i].id = FIELD_GET(ARM_SMMU_SMR_ID, smr);
> + smmu->smrs[i].mask = FIELD_GET(ARM_SMMU_SMR_MASK, smr);
> + smmu->smrs[i].valid = true;
> +
> + smmu->s2crs[i].type = S2CR_TYPE_BYPASS;
> + smmu->s2crs[i].privcfg = S2CR_PRIVCFG_DEFAULT;
> + smmu->s2crs[i].cbndx = 0xff;
> + }
> + }
> +
> + return 0;
> +}
> +
> static int qcom_smmu_def_domain_type(struct device *dev)
> {
> const struct of_device_id *match =
> @@ -61,6 +83,7 @@ static int qcom_smmu500_reset(struct arm_smmu_device *smmu)
> }
>
> static const struct arm_smmu_impl qcom_smmu_impl = {
> + .cfg_probe = qcom_smmu_cfg_probe,
> .def_domain_type = qcom_smmu_def_domain_type,
> .reset = qcom_smmu500_reset,
> };
>
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