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Message-Id: <20201020031814.17939-1-yifeng.zhao@rock-chips.com>
Date: Tue, 20 Oct 2020 11:18:11 +0800
From: Yifeng Zhao <yifeng.zhao@...k-chips.com>
To: miquel.raynal@...tlin.com, richard@....at, vigneshr@...com,
robh+dt@...nel.org
Cc: devicetree@...r.kernel.org, linux-mtd@...ts.infradead.org,
heiko@...ech.de, linux-rockchip@...ts.infradead.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
Yifeng Zhao <yifeng.zhao@...k-chips.com>
Subject: [PATCH v12 5/8] arm64: dts: rockchip: Add NFC node for PX30 SoC
Add NAND FLASH Controller(NFC) node for PX30 SoC.
Signed-off-by: Yifeng Zhao <yifeng.zhao@...k-chips.com>
---
(no changes since v1)
arch/arm64/boot/dts/rockchip/px30.dtsi | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi
index 2695ea8cda14..6cd67e80d623 100644
--- a/arch/arm64/boot/dts/rockchip/px30.dtsi
+++ b/arch/arm64/boot/dts/rockchip/px30.dtsi
@@ -973,6 +973,21 @@
status = "disabled";
};
+ nfc: nand-controller@...b0000 {
+ compatible = "rockchip,px30-nfc";
+ reg = <0x0 0xff3b0000 0x0 0x4000>;
+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
+ clock-names = "ahb", "nfc";
+ assigned-clocks = <&cru SCLK_NANDC>;
+ assigned-clock-rates = <150000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_cs0
+ &flash_rdn &flash_rdy &flash_wrn &flash_dqs>;
+ power-domains = <&power PX30_PD_MMC_NAND>;
+ status = "disabled";
+ };
+
gpu: gpu@...00000 {
compatible = "rockchip,px30-mali", "arm,mali-bifrost";
reg = <0x0 0xff400000 0x0 0x4000>;
--
2.17.1
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