linux-kernel - Re: [PATCH v2 3/6] spi: cadence-quadspi: Add multi-chipselect support for Intel LGM SoC

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Message-ID: <20201021144650.GG4497@sirena.org.uk>
Date:   Wed, 21 Oct 2020 15:46:50 +0100
From:   Mark Brown <broonie@...nel.org>
To:     "Ramuthevar,Vadivel MuruganX" 
        <vadivel.muruganx.ramuthevar@...ux.intel.com>
Cc:     vigneshr@...com, tudor.ambarus@...rochip.com,
        linux-kernel@...r.kernel.org, linux-spi@...r.kernel.org,
        robh+dt@...nel.org, devicetree@...r.kernel.org,
        miquel.raynal@...tlin.com, simon.k.r.goldschmidt@...il.com,
        dinguyen@...nel.org, richard@....at, cheol.yong.kim@...el.com,
        qi-ming.wu@...el.com
Subject: Re: [PATCH v2 3/6] spi: cadence-quadspi: Add multi-chipselect
 support for Intel LGM SoC

On Wed, Oct 21, 2020 at 10:55:04AM +0800, Ramuthevar,Vadivel MuruganX wrote:

> Add multiple chipselect support for Intel LGM SoCs,
> currently QSPI-NOR and QSPI-NAND supported.

> +	if (ddata->hwcaps_mask & CQSPI_SUPPORTS_MULTI_CHIPSELECT)
> +		master->num_chipselect = cqspi->num_chipselect;

I'm not seeing anywhere else where we reference num_chipselect in this
patch - we parse the value, set it in the SPI controller and then never
otherwise use it?  This makes me wonder if the property is really
mandatory.  If it is then there should be something in the binding
document saying that it's required when the compatible is your new
compatible string, that way the validation can verify that the property
is present in DTs including this controller.

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