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Message-ID: <CALAqxLVyszFbOnWAOMekQuWbGgmMZpEfFiY6gyAPYmGXPz5sHA@mail.gmail.com>
Date: Wed, 21 Oct 2020 14:33:41 -0700
From: John Stultz <john.stultz@...aro.org>
To: Thinh Nguyen <Thinh.Nguyen@...opsys.com>
Cc: lkml <linux-kernel@...r.kernel.org>, Yu Chen <chenyu56@...wei.com>,
Felipe Balbi <balbi@...nel.org>,
Tejas Joglekar <Tejas.Joglekar@...opsys.com>,
Yang Fei <fei.yang@...el.com>,
YongQin Liu <yongqin.liu@...aro.org>,
Andrzej Pietrasiewicz <andrzej.p@...labora.com>,
Jun Li <lijun.kernel@...il.com>,
Mauro Carvalho Chehab <mchehab+huawei@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
"linux-usb@...r.kernel.org" <linux-usb@...r.kernel.org>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>
Subject: Re: [RFC][PATCH] usb: dwc3: Add quirk to trigger a GCTL soft reset
for Hisilicon Kirin Soc Platform
On Wed, Oct 21, 2020 at 12:14 PM Thinh Nguyen <Thinh.Nguyen@...opsys.com> wrote:
>
> John Stultz wrote:
> > From: Yu Chen <chenyu56@...wei.com>
> >
> > With the current dwc3 code on the HiKey960 we often see the
> > COREIDLE flag get stuck off in __dwc3_gadget_start(), which
> > seems to prevent the reset irq and causes the USB gadget to
> > fail to initialize.
> >
> > We had seen occasional initialization failures with older
> > kernels but with recent 5.x era kernels it seemed to be becoming
> > much more common, so I dug back through some older trees and
> > realized I dropped this quirk from Yu Chen during upstreaming
> > as I couldn't provide a proper rational for it and it didn't
> > seem to be necessary. I now realize I was wrong.
> >
> > On the upside, I can now understand more why such a quirk is
> > needed.
>
> This shouldn't be a quirk. It's part of the programming guide when
> switching mode in DRD. I don't know how we missed this.
Ah! That's great, as it should simplify the patch a bit and avoid
introducing another dt bindings!
> > diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> > index bdf0925da6b6..b138c67e3892 100644
> > --- a/drivers/usb/dwc3/core.c
> > +++ b/drivers/usb/dwc3/core.c
> > @@ -114,6 +114,19 @@ void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode)
> > dwc->current_dr_role = mode;
> > }
> >
> > +static void dwc3_gctl_core_soft_reset(struct dwc3 *dwc)
> > +{
> > + int reg;
> > +
> > + reg = dwc3_readl(dwc->regs, DWC3_GCTL);
> > + reg |= (DWC3_GCTL_CORESOFTRESET);
> > + dwc3_writel(dwc->regs, DWC3_GCTL, reg);
> > +
> > + reg = dwc3_readl(dwc->regs, DWC3_GCTL);
> > + reg &= ~(DWC3_GCTL_CORESOFTRESET);
> > + dwc3_writel(dwc->regs, DWC3_GCTL, reg);
> > +}
> > +
> > static void __dwc3_set_mode(struct work_struct *work)
> > {
> > struct dwc3 *dwc = work_to_dwc(work);
> > @@ -178,6 +191,10 @@ static void __dwc3_set_mode(struct work_struct *work)
> > }
> > break;
> > case DWC3_GCTL_PRTCAP_DEVICE:
> > + /* Execute a GCTL Core Soft Reset when switch mode */
> > + if (dwc->gctl_reset_quirk)
> > + dwc3_gctl_core_soft_reset(dwc);
> > +
>
> This should be done before dwc3_set_prtcap(), and this applies when
> switching from device to host mode also. Make sure to check if the
> controller is DRD before doing this.
Sorry, by checking that the controller is DRD, I'm not sure exactly
what you mean.
Checking DWC3_GHWPARAMS0_MODE_DRD? Or something else?
Thanks so much for the review and feedback!
-john
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