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Date:   Thu, 22 Oct 2020 10:54:53 +0300
From:   Felipe Balbi <balbi@...nel.org>
To:     John Stultz <john.stultz@...aro.org>,
        lkml <linux-kernel@...r.kernel.org>
Cc:     Yu Chen <chenyu56@...wei.com>,
        Tejas Joglekar <tejas.joglekar@...opsys.com>,
        Yang Fei <fei.yang@...el.com>,
        YongQin Liu <yongqin.liu@...aro.org>,
        Andrzej Pietrasiewicz <andrzej.p@...labora.com>,
        Thinh Nguyen <thinhn@...opsys.com>,
        Jun Li <lijun.kernel@...il.com>,
        Mauro Carvalho Chehab <mchehab+huawei@...nel.org>,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        linux-usb@...r.kernel.org, John Stultz <john.stultz@...aro.org>
Subject: Re: [PATCH v2] usb: dwc3: Trigger a GCTL soft reset when switching
 modes in DRD


Hi,

John Stultz <john.stultz@...aro.org> writes:
> From: Yu Chen <chenyu56@...wei.com>
>
> With the current dwc3 code on the HiKey960 we often see the
> COREIDLE flag get stuck off in __dwc3_gadget_start(), which
> seems to prevent the reset irq and causes the USB gadget to
> fail to initialize.
>
> We had seen occasional initialization failures with older
> kernels but with recent 5.x era kernels it seemed to be becoming
> much more common, so I dug back through some older trees and
> realized I dropped this quirk from Yu Chen during upstreaming
> as I couldn't provide a proper rational for it and it didn't
> seem to be necessary. I now realize I was wrong.

This keeps coming back every few years. It has never been necessary so
far. Why is it necessary now? The only thing we need to do is verify
which registers are shadowed between host and peripheral roles and cache
only those registers.

A full soft reset will take a while and is likely to create other
issues.

-- 
balbi

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