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Message-ID: <1603370247-30437-7-git-send-email-weiyi.lu@mediatek.com>
Date:   Thu, 22 Oct 2020 20:36:59 +0800
From:   Weiyi Lu <weiyi.lu@...iatek.com>
To:     Matthias Brugger <matthias.bgg@...il.com>,
        Rob Herring <robh@...nel.org>, Stephen Boyd <sboyd@...nel.org>,
        Nicolas Boichat <drinkcat@...omium.org>
CC:     <linux-arm-kernel@...ts.infradead.org>,
        <linux-kernel@...r.kernel.org>,
        <linux-mediatek@...ts.infradead.org>, <linux-clk@...r.kernel.org>,
        <srv_heupstream@...iatek.com>, Weiyi Lu <weiyi.lu@...iatek.com>
Subject: [PATCH v4 06/34] dt-bindings: ARM: Mediatek: Add new document bindings of vdecsys soc controller

This patch adds the new binding documentation of vdecsys soc controller
for Mediatek MT8192.

Signed-off-by: Weiyi Lu <weiyi.lu@...iatek.com>
---
 .../arm/mediatek/mediatek,vdecsys-soc.yaml         | 38 ++++++++++++++++++++++
 1 file changed, 38 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys-soc.yaml

diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys-soc.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys-soc.yaml
new file mode 100644
index 0000000..082f22e
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys-soc.yaml
@@ -0,0 +1,38 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/mediatek/mediatek,vdecsys-soc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek VDECSYS SOC Controller
+
+maintainers:
+  - Weiyi Lu <weiyi.lu@...iatek.com>
+
+description:
+  The Mediatek vdecsys soc controller provides functional configurations and clocks to the system.
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - mediatek,mt8192-vdecsys_soc
+      - const: syscon
+
+  reg:
+    maxItems: 1
+
+  '#clock-cells':
+    const: 1
+
+required:
+  - compatible
+  - reg
+
+examples:
+  - |
+    vdecsys_soc: syscon@...0f000 {
+        compatible = "mediatek,mt8192-vdecsys_soc", "syscon";
+        reg = <0 0x1600f000 0 0x1000>;
+        #clock-cells = <1>;
+    };
-- 
1.8.1.1.dirty

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