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Message-Id: <20201023075744.26200-4-m.szyprowski@samsung.com>
Date: Fri, 23 Oct 2020 09:57:41 +0200
From: Marek Szyprowski <m.szyprowski@...sung.com>
To: linux-samsung-soc@...r.kernel.org, linux-pci@...r.kernel.org
Cc: devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
Jaehoon Chung <jh80.chung@...sung.com>,
Marek Szyprowski <m.szyprowski@...sung.com>,
Jingoo Han <jingoohan1@...il.com>,
Krzysztof Kozlowski <krzk@...nel.org>,
Bjorn Helgaas <bhelgaas@...gle.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
Vinod Koul <vkoul@...nel.org>,
Kishon Vijay Abraham I <kishon@...com>,
Rob Herring <robh+dt@...nel.org>
Subject: [PATCH v2 3/6] dt-bindings: phy: add the samsung,exynos-pcie-phy
binding
Add dt-bindings for the Samsung Exynos PCIe PHY controller (Exynos5433
variant). Based on the text dt-binding posted by Jaehoon Chung.
Signed-off-by: Marek Szyprowski <m.szyprowski@...sung.com>
---
.../bindings/phy/samsung,exynos-pcie-phy.yaml | 51 +++++++++++++++++++
1 file changed, 51 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/samsung,exynos-pcie-phy.yaml
diff --git a/Documentation/devicetree/bindings/phy/samsung,exynos-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/samsung,exynos-pcie-phy.yaml
new file mode 100644
index 000000000000..ac0af40be52d
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/samsung,exynos-pcie-phy.yaml
@@ -0,0 +1,51 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/samsung,exynos-pcie-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung SoC series PCIe PHY Device Tree Bindings
+
+maintainers:
+ - Marek Szyprowski <m.szyprowski@...sung.com>
+ - Jaehoon Chung <jh80.chung@...sung.com>
+
+properties:
+ "#phy-cells":
+ const: 0
+
+ compatible:
+ const: samsung,exynos5433-pcie-phy
+
+ reg:
+ maxItems: 1
+
+ samsung,pmu-syscon:
+ $ref: '/schemas/types.yaml#/definitions/phandle'
+ description: phandle for PMU system controller interface, used to
+ control PMU registers bits for PCIe PHY
+
+ samsung,fsys-sysreg:
+ $ref: '/schemas/types.yaml#/definitions/phandle'
+ description: phandle for FSYS sysreg interface, used to control
+ sysreg registers bits for PCIe PHY
+
+required:
+ - "#phy-cells"
+ - compatible
+ - reg
+ - samsung,pmu-syscon
+ - samsung,fsys-sysreg
+
+additionalProperties: false
+
+examples:
+ - |
+ pcie_phy: pcie-phy@...80000 {
+ compatible = "samsung,exynos5433-pcie-phy";
+ reg = <0x15680000 0x1000>;
+ samsung,pmu-syscon = <&pmu_system_controller>;
+ samsung,fsys-sysreg = <&syscon_fsys>;
+ #phy-cells = <0>;
+ };
+...
--
2.17.1
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