Message-ID: <C53CAD52-38F8-47D7-A5BE-4F470532EF20@infradead.org>
Date:   Fri, 23 Oct 2020 11:10:39 +0100
From:   David Woodhouse <dwmw2@...radead.org>
To:     Thomas Gleixner <tglx@...utronix.de>, x86@...nel.org
CC:     kvm <kvm@...r.kernel.org>, Paolo Bonzini <pbonzini@...hat.com>,
        linux-kernel <linux-kernel@...r.kernel.org>,
        linux-hyperv@...r.kernel.org
Subject: Re: [PATCH v2 8/8] x86/ioapic: Generate RTE directly from parent irqchip's MSI message



On 22 October 2020 22:43:52 BST, Thomas Gleixner <tglx@...utronix.de> wrote:
>On Fri, Oct 09 2020 at 11:46, David Woodhouse wrote:
>
>@@ -45,12 +45,11 @@ enum irq_alloc_type {
> };
>
>> +static void mp_swizzle_msi_dest_bits(struct irq_data *irq_data, void
>*_entry)
>> +{
>> +	struct msi_msg msg;
>> +	u32 *entry = _entry;
>
>Why is this a void * argument and then converting it to a u32 *? Just
>to
>make that function completely unreadable?

It makes the callers slightly more readable, not having to cast to uint32_t* from the struct.

I did ponder defining a new struct with bitfields named along the lines of 'msi_addr_bits_19_to_4', but that seemed like overkill.

>> +
>> +	irq_chip_compose_msi_msg(irq_data, &msg);
>
>Lacks a comment. Also mp_swizzle... is a misnomer as this invokes the
>msi compose function which is not what the function name suggests.

It's got a four-line comment right there after it as we use the bits we got from it.

>> +	/*
>> +	 * They're in a bit of a random order for historical reasons, but
>> +	 * the IO/APIC is just a device for turning interrupt lines into
>> +	 * MSIs, and various bits of the MSI addr/data are just swizzled
>> +	 * into/from the bits of Redirection Table Entry.
>> +	 */
>> +	entry[0] &= 0xfffff000;
>> +	entry[0] |= (msg.data & (MSI_DATA_DELIVERY_MODE_MASK |
>> +				 MSI_DATA_VECTOR_MASK));
>> +	entry[0] |= (msg.address_lo & MSI_ADDR_DEST_MODE_MASK) << 9;
>> +
>> +	entry[1] &= 0xffff;
>> +	entry[1] |= (msg.address_lo & MSI_ADDR_DEST_ID_MASK) << 12;
>
>Sorry, but this is unreviewable gunk.

Crap. Sure, want to look at the I/OAPIC and MSI documentation and observe that it's just shifting bits around and "these bits go there, those bits go here..." but there's no magic which will make that go away. At some point you end up swizzling bits around with seemingly random bitmasks and shifts which you have to have worked out from the docs.

Now that I killed off the various IOMMU bits which also horrifically touch the RTE directly, perhaps there is more scope for faffing around with it differently, but it won't really change much. It's just urinating into the atmospheric disturbance.


>Aside of that it works magically because polarity,trigger and mask bit
>have been set up before. But of course a comment about this is
>completely overrated.

Well yes, there's a lot about the I/OAPIC code which is a bit horrid but this patch is doing just one thing: making the bits get from e.g. cfg->dest_apicid and cfg->vector into the RTE in a generic fashion which does the right thing for IR too. Other cleanups are somewhat orthogonal, but yes it's a good spot that one of these was somewhat redundant in the first place. We could fix that up in a separate patch which comes first perhaps.

If we're starting to clean up I/OAPIC code I'd like to take a long hard look at the level ack code paths, and the fact that we have separate ack_apic_irq and apic_ack_irq functions (or something like that; on phone now) which do different things. Perhaps the order (or the capitals on APIC which one of them has) makes it sane and meaningful for them both to exist and do different things?

I also note the Hyper-V "remapping" takes the IR code path and I'm not sure that's OK. Because of the complete lack of overall documentation on what it's all doing and why.

-- 
Sent from my Android device with K-9 Mail. Please excuse my brevity.

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