linux-kernel - Re: [PATCH v2 2/4] arm: mm: reordering memory type table

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Message-ID: <20201023101640.GA1551@shell.armlinux.org.uk>
Date:   Fri, 23 Oct 2020 11:16:40 +0100
From:   Russell King - ARM Linux admin <linux@...linux.org.uk>
To:     Miles Chen <miles.chen@...iatek.com>
Cc:     Catalin Marinas <catalin.marinas@....com>,
        Minchan Kim <minchan@...nel.org>,
        linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
        linux-mediatek@...ts.infradead.org, wsd_upstream@...iatek.com,
        Will Deacon <will.deacon@....com>,
        Steve Capper <steve.capper@...aro.org>,
        Simon Horman <horms@...ge.net.au>,
        Suren Baghdasaryan <surenb@...gle.com>
Subject: Re: [PATCH v2 2/4] arm: mm: reordering memory type table

On Fri, Oct 23, 2020 at 05:14:35PM +0800, Miles Chen wrote:
> From: Minchan Kim <minchan@...nel.org>
> 
> To use bit 5 in page table as L_PTE_SPECIAL, we need a room for that.
> It seems we don't need 4 bits for the memory type with ARMv6+.
> If it's true, let's reorder bits to make bit 5 free.
> 
> We will use the bit for L_PTE_SPECIAL in next patch.
> 
> A note from Catalin in [1]:
> "
> > Anyway, on ARMv7 or ARMv6+LPAE, the non-shared device gets mapped to
> > shared device in hardware. Looking through the arm32 code, it seems that
> > MT_DEVICE_NONSHARED is used by arch/arm/mach-shmobile/setup-r8a7779.c
> > and IIUC that's a v7 platform (R-Car H1, Cortex-A9). I think the above
> > should be defined to L_PTE_MT_DEV_SHARED, unless I miss any place where
> > DEV_NONSHARED is relevant on ARMv6 (adding Simon to confirm on shmbile).
> "
> 
> [1] https://lore.kernel.org/patchwork/patch/986574/
> 
> Cc: Russell King <linux@...linux.org.uk>
> Cc: Catalin Marinas <catalin.marinas@....com>
> Cc: Will Deacon <will.deacon@....com>
> Cc: Steve Capper <steve.capper@...aro.org>
> Cc: Simon Horman <horms@...ge.net.au>
> Cc: Minchan Kim <minchan@...nel.org>
> Cc: Suren Baghdasaryan <surenb@...gle.com>
> Signed-off-by: Minchan Kim <minchan@...nel.org>
> Signed-off-by: Miles Chen <miles.chen@...iatek.com>
> ---
>  arch/arm/include/asm/pgtable-2level.h | 21 +++++++++++++++++----
>  arch/arm/mm/proc-macros.S             |  4 ++--
>  2 files changed, 19 insertions(+), 6 deletions(-)
> 
> diff --git a/arch/arm/include/asm/pgtable-2level.h b/arch/arm/include/asm/pgtable-2level.h
> index 27a8635abea0..cdcd55cca37d 100644
> --- a/arch/arm/include/asm/pgtable-2level.h
> +++ b/arch/arm/include/asm/pgtable-2level.h
> @@ -161,14 +161,27 @@
>  #define L_PTE_MT_BUFFERABLE	(_AT(pteval_t, 0x01) << 2)	/* 0001 */
>  #define L_PTE_MT_WRITETHROUGH	(_AT(pteval_t, 0x02) << 2)	/* 0010 */
>  #define L_PTE_MT_WRITEBACK	(_AT(pteval_t, 0x03) << 2)	/* 0011 */
> +#define L_PTE_MT_DEV_SHARED	(_AT(pteval_t, 0x04) << 2)	/* 0100 */
> +#define L_PTE_MT_VECTORS	(_AT(pteval_t, 0x05) << 2)	/* 0101 */
>  #define L_PTE_MT_MINICACHE	(_AT(pteval_t, 0x06) << 2)	/* 0110 (sa1100, xscale) */
>  #define L_PTE_MT_WRITEALLOC	(_AT(pteval_t, 0x07) << 2)	/* 0111 */
> -#define L_PTE_MT_DEV_SHARED	(_AT(pteval_t, 0x04) << 2)	/* 0100 */
> -#define L_PTE_MT_DEV_NONSHARED	(_AT(pteval_t, 0x0c) << 2)	/* 1100 */

Sorry, no, this isn't going to work.

The lower two bits of this (bits 2 and 3) are explicitly designed to fit
the C and B bits used in older architectures. Changing L_PTE_MT_VECTORS
from having value '11' to '01' changes the functionality on older CPUs.

-- 
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