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Message-Id: <20201023133130.194140-3-fparent@baylibre.com>
Date: Fri, 23 Oct 2020 15:31:27 +0200
From: Fabien Parent <fparent@...libre.com>
To: linux-mediatek@...ts.infradead.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org, dri-devel@...ts.freedesktop.org
Cc: matthias.bgg@...il.com, robh+dt@...nel.org, daniel@...ll.ch,
airlied@...ux.ie, p.zabel@...gutronix.de, chunkuang.hu@...nel.org,
Fabien Parent <fparent@...libre.com>
Subject: [PATCH v2 2/5] dt-bindings: display: mediatek: dsi: add documentation for MT8167 SoC
Add binding documentation for the MT8167 SoC.
Signed-off-by: Fabien Parent <fparent@...libre.com>
---
Changelog:
V2: removed part that added a new clock
.../devicetree/bindings/display/mediatek/mediatek,dsi.txt | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
index f06f24d405a5..6a10de812158 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
@@ -7,7 +7,7 @@ channel output.
Required properties:
- compatible: "mediatek,<chip>-dsi"
-- the supported chips are mt2701, mt7623, mt8173 and mt8183.
+- the supported chips are mt2701, mt7623, mt8167, mt8173 and mt8183.
- reg: Physical base address and length of the controller's registers
- interrupts: The interrupt signal from the function block.
- clocks: device clocks
@@ -26,7 +26,7 @@ The MIPI TX configuration module controls the MIPI D-PHY.
Required properties:
- compatible: "mediatek,<chip>-mipi-tx"
-- the supported chips are mt2701, 7623, mt8173 and mt8183.
+- the supported chips are mt2701, 7623, mt8167, mt8173 and mt8183.
- reg: Physical base address and length of the controller's registers
- clocks: PLL reference clock
- clock-output-names: name of the output clock line to the DSI encoder
--
2.28.0
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