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Message-Id: <20201025221735.3062-26-digetx@gmail.com>
Date: Mon, 26 Oct 2020 01:17:08 +0300
From: Dmitry Osipenko <digetx@...il.com>
To: Thierry Reding <thierry.reding@...il.com>,
Jonathan Hunter <jonathanh@...dia.com>,
Georgi Djakov <georgi.djakov@...aro.org>,
Rob Herring <robh+dt@...nel.org>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>,
Peter De Schrijver <pdeschrijver@...dia.com>,
MyungJoo Ham <myungjoo.ham@...sung.com>,
Kyungmin Park <kyungmin.park@...sung.com>,
Chanwoo Choi <cw00.choi@...sung.com>,
Mikko Perttunen <cyndis@...si.fi>,
Viresh Kumar <vireshk@...nel.org>,
Peter Geis <pgwipeout@...il.com>,
Nicolas Chauvet <kwizart@...il.com>,
Krzysztof Kozlowski <krzk@...nel.org>
Cc: linux-tegra@...r.kernel.org, linux-pm@...r.kernel.org,
linux-kernel@...r.kernel.org, dri-devel@...ts.freedesktop.org,
devicetree@...r.kernel.org
Subject: [PATCH v6 25/52] ARM: tegra: Add DVFS properties to Tegra20 EMC device-tree node
Add EMC OPP DVFS/DFS tables and emc-stats subdev that will be used for
dynamic memory bandwidth scaling, while EMC itself will perform voltage
scaling. Update board device-trees with optional EMC core supply and
remove unsupported OPPs.
Signed-off-by: Dmitry Osipenko <digetx@...il.com>
---
.../boot/dts/tegra20-acer-a500-picasso.dts | 12 ++
arch/arm/boot/dts/tegra20-colibri.dtsi | 8 +
arch/arm/boot/dts/tegra20-paz00.dts | 10 +
.../arm/boot/dts/tegra20-peripherals-opp.dtsi | 181 ++++++++++++++++++
arch/arm/boot/dts/tegra20.dtsi | 12 +-
5 files changed, 222 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/tegra20-peripherals-opp.dtsi
diff --git a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts
index a0b829738e8f..f5c1591c8ea8 100644
--- a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts
+++ b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts
@@ -1058,9 +1058,21 @@ map0 {
};
};
+ emc_opp_table0 {
+ /delete-node/ opp@...000000;
+ /delete-node/ opp@...000000;
+ };
+
+ emc_opp_table1 {
+ /delete-node/ opp@...000000;
+ /delete-node/ opp@...000000;
+ };
+
memory-controller@...0f400 {
nvidia,use-ram-code;
+ core-supply = <&vdd_core>;
+
emc-tables@0 {
nvidia,ram-code = <0>; /* elpida-8gb */
diff --git a/arch/arm/boot/dts/tegra20-colibri.dtsi b/arch/arm/boot/dts/tegra20-colibri.dtsi
index 6162d193e12c..78a2210bf9ae 100644
--- a/arch/arm/boot/dts/tegra20-colibri.dtsi
+++ b/arch/arm/boot/dts/tegra20-colibri.dtsi
@@ -611,6 +611,14 @@ i2c-thermtrip {
};
};
+ emc_opp_table0 {
+ /delete-node/ opp@...000000;
+ };
+
+ emc_opp_table1 {
+ /delete-node/ opp@...000000;
+ };
+
memory-controller@...0f400 {
emc-table@...50 {
reg = <83250>;
diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts
index ada2bed8b1b5..7b9f0f279744 100644
--- a/arch/arm/boot/dts/tegra20-paz00.dts
+++ b/arch/arm/boot/dts/tegra20-paz00.dts
@@ -311,9 +311,19 @@ nvec@...0c500 {
reset-names = "i2c";
};
+ emc_opp_table0 {
+ /delete-node/ opp@...000000;
+ };
+
+ emc_opp_table1 {
+ /delete-node/ opp@...000000;
+ };
+
memory-controller@...0f400 {
nvidia,use-ram-code;
+ core-supply = <&core_vdd_reg>;
+
emc-tables@0 {
nvidia,ram-code = <0x0>;
#address-cells = <1>;
diff --git a/arch/arm/boot/dts/tegra20-peripherals-opp.dtsi b/arch/arm/boot/dts/tegra20-peripherals-opp.dtsi
new file mode 100644
index 000000000000..d10c61107702
--- /dev/null
+++ b/arch/arm/boot/dts/tegra20-peripherals-opp.dtsi
@@ -0,0 +1,181 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/ {
+ emc_icc_dvfs_opp_table: emc_opp_table0 {
+ compatible = "operating-points-v2";
+
+ opp@...00000 {
+ opp-microvolt = <950000 950000 1300000>;
+ opp-hz = /bits/ 64 <36000000>;
+ };
+
+ opp@...00000 {
+ opp-microvolt = <950000 950000 1300000>;
+ opp-hz = /bits/ 64 <47500000>;
+ };
+
+ opp@...00000 {
+ opp-microvolt = <950000 950000 1300000>;
+ opp-hz = /bits/ 64 <50000000>;
+ };
+
+ opp@...00000 {
+ opp-microvolt = <950000 950000 1300000>;
+ opp-hz = /bits/ 64 <54000000>;
+ };
+
+ opp@...00000 {
+ opp-microvolt = <950000 950000 1300000>;
+ opp-hz = /bits/ 64 <57000000>;
+ };
+
+ opp@...000000 {
+ opp-microvolt = <1000000 1000000 1300000>;
+ opp-hz = /bits/ 64 <100000000>;
+ };
+
+ opp@...000000 {
+ opp-microvolt = <1000000 1000000 1300000>;
+ opp-hz = /bits/ 64 <108000000>;
+ };
+
+ opp@...666000 {
+ opp-microvolt = <1000000 1000000 1300000>;
+ opp-hz = /bits/ 64 <126666000>;
+ };
+
+ opp@...000000 {
+ opp-microvolt = <1000000 1000000 1300000>;
+ opp-hz = /bits/ 64 <150000000>;
+ };
+
+ opp@...000000 {
+ opp-microvolt = <1000000 1000000 1300000>;
+ opp-hz = /bits/ 64 <190000000>;
+ };
+
+ opp@...000000 {
+ opp-microvolt = <1000000 1000000 1300000>;
+ opp-hz = /bits/ 64 <216000000>;
+ };
+
+ opp@...000000 {
+ opp-microvolt = <1000000 1000000 1300000>;
+ opp-hz = /bits/ 64 <300000000>;
+ };
+
+ opp@...000000 {
+ opp-microvolt = <1000000 1000000 1300000>;
+ opp-hz = /bits/ 64 <333000000>;
+ };
+
+ opp@...000000 {
+ opp-microvolt = <1100000 1100000 1300000>;
+ opp-hz = /bits/ 64 <380000000>;
+ };
+
+ opp@...000000 {
+ opp-microvolt = <1200000 1200000 1300000>;
+ opp-hz = /bits/ 64 <600000000>;
+ };
+
+ opp@...000000 {
+ opp-microvolt = <1200000 1200000 1300000>;
+ opp-hz = /bits/ 64 <666000000>;
+ };
+
+ opp@...000000 {
+ opp-microvolt = <1300000 1300000 1300000>;
+ opp-hz = /bits/ 64 <760000000>;
+ };
+ };
+
+ emc_bw_dfs_opp_table: emc_opp_table1 {
+ compatible = "operating-points-v2";
+
+ opp@...00000 {
+ opp-hz = /bits/ 64 <36000000>;
+ opp-peak-kBps = <144000>;
+ };
+
+ opp@...00000 {
+ opp-hz = /bits/ 64 <47500000>;
+ opp-peak-kBps = <190000>;
+ };
+
+ opp@...00000 {
+ opp-hz = /bits/ 64 <50000000>;
+ opp-peak-kBps = <200000>;
+ };
+
+ opp@...00000 {
+ opp-hz = /bits/ 64 <54000000>;
+ opp-peak-kBps = <216000>;
+ };
+
+ opp@...00000 {
+ opp-hz = /bits/ 64 <57000000>;
+ opp-peak-kBps = <228000>;
+ };
+
+ opp@...000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ opp-peak-kBps = <400000>;
+ };
+
+ opp@...000000 {
+ opp-hz = /bits/ 64 <108000000>;
+ opp-peak-kBps = <432000>;
+ };
+
+ opp@...666000 {
+ opp-hz = /bits/ 64 <126666000>;
+ opp-peak-kBps = <506664>;
+ };
+
+ opp@...000000 {
+ opp-hz = /bits/ 64 <150000000>;
+ opp-peak-kBps = <600000>;
+ };
+
+ opp@...000000 {
+ opp-hz = /bits/ 64 <190000000>;
+ opp-peak-kBps = <760000>;
+ };
+
+ opp@...000000 {
+ opp-hz = /bits/ 64 <216000000>;
+ opp-peak-kBps = <864000>;
+ };
+
+ opp@...000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-peak-kBps = <1200000>;
+ };
+
+ opp@...000000 {
+ opp-hz = /bits/ 64 <333000000>;
+ opp-peak-kBps = <1332000>;
+ };
+
+ opp@...000000 {
+ opp-hz = /bits/ 64 <380000000>;
+ opp-peak-kBps = <1520000>;
+ };
+
+ opp@...000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-peak-kBps = <2400000>;
+ };
+
+ opp@...000000 {
+ opp-hz = /bits/ 64 <666000000>;
+ opp-peak-kBps = <2664000>;
+ };
+
+ opp@...000000 {
+ opp-hz = /bits/ 64 <760000000>;
+ opp-peak-kBps = <3040000>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 8f8ad81916e7..8a90d96c8773 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -6,6 +6,8 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/soc/tegra-pmc.h>
+#include "tegra20-peripherals-opp.dtsi"
+
/ {
compatible = "nvidia,tegra20";
interrupt-parent = <&lic>;
@@ -656,7 +658,7 @@ mc: memory-controller@...0f000 {
};
emc: memory-controller@...0f400 {
- compatible = "nvidia,tegra20-emc";
+ compatible = "nvidia,tegra20-emc", "simple-mfd";
reg = <0x7000f400 0x400>;
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA20_CLK_EMC>;
@@ -664,7 +666,15 @@ emc: memory-controller@...0f400 {
#size-cells = <0>;
#interconnect-cells = <0>;
+ operating-points-v2 = <&emc_icc_dvfs_opp_table>;
nvidia,memory-controller = <&mc>;
+
+ emc-stats {
+ compatible = "nvidia,tegra20-emc-statistics";
+ operating-points-v2 = <&emc_bw_dfs_opp_table>;
+ interconnects = <&mc TEGRA20_MC_MPCORER &emc>;
+ interconnect-names = "cpu-read";
+ };
};
fuse@...0f800 {
--
2.27.0
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