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Date:   Mon, 26 Oct 2020 22:14:10 +0300
From:   Dmitry Osipenko <>
To:     Krzysztof Kozlowski <>,
        Chanwoo Choi <>
Cc:     Thierry Reding <>,
        Jonathan Hunter <>,
        Georgi Djakov <>,
        Rob Herring <>,
        Michael Turquette <>,
        Stephen Boyd <>,
        Peter De Schrijver <>,
        MyungJoo Ham <>,
        Kyungmin Park <>,
        Mikko Perttunen <>,
        Viresh Kumar <>,
        Peter Geis <>,
        Nicolas Chauvet <>,,,,,
Subject: Re: [PATCH v6 00/52] Introduce memory interconnect for NVIDIA Tegra

26.10.2020 18:08, Krzysztof Kozlowski пишет:
> On Mon, Oct 26, 2020 at 01:16:43AM +0300, Dmitry Osipenko wrote:
>> Hello,
>> This series brings initial support for memory interconnect to Tegra20,
>> Tegra30 and Tegra124 SoCs.
>> For the starter only display controllers and devfreq devices are getting
>> interconnect API support, others could be supported later on. The display
>> controllers have the biggest demand for interconnect API right now because
>> dynamic memory frequency scaling can't be done safely without taking into
>> account bandwidth requirement from the displays. In particular this series
>> fixes distorted display output on T30 Ouya and T124 TK1 devices.
> Hi,
> You introduced in v6 multiple new patches. Could you describe the
> dependencies, if any?


The v6 dropped some older patches and replaced them with the new
patches. Previously I wanted to postpone the more complex changes for
later times, like supporting OPP tables and DVFS, but then the review
started to take more time than was expected and there was enough time to
complete those features.

There are five basic sets of patches:

	1. DT bindings
	2. DT changes
	3. SoC, clk and memory
	4. devfreq
	5. DRM

Each set could be applied separately.

Memory patches have a build dependency on the SoC and clk patches.

The "tegra-mc: Add interconnect framework" and "Add and use
devm_tegra_get_memory_controller()" are the root build dependencies for
all memory/ patches. Other patches are grouped per SoC generation
(Tegra20/30/124), patches within a SoC-gen group are interdependent.

I suppose the best variant would be to merge the whole series via
tegra-tree in order to preserve logical order of the patches. Although,
merging each set of patches separately also should be okay to do.

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