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Message-ID: <20201026063902.14744-2-vidyas@nvidia.com>
Date: Mon, 26 Oct 2020 12:09:02 +0530
From: Vidya Sagar <vidyas@...dia.com>
To: <robh+dt@...nel.org>, <thierry.reding@...il.com>,
<jonathanh@...dia.com>, <jckuo@...dia.com>,
<kyarlagadda@...dia.com>, <lorenzo.pieralisi@....com>,
<amurray@...goodpenguin.co.uk>
CC: <linux-gpio@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-tegra@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<kthota@...dia.com>, <mmaddireddy@...dia.com>, <vidyas@...dia.com>,
<sagar.tv@...il.com>
Subject: [PATCH 2/2] arm64: tegra: Fix DT binding for IO High Voltage entry
Fix the device-tree entry that represents I/O High Voltage property
by replacing 'nvidia,io-high-voltage' with 'nvidia,io-hv' as the former
entry is deprecated.
Fixes: dbb72e2c305b ("arm64: tegra: Add configuration for PCIe C5 sideband signals")
Signed-off-by: Vidya Sagar <vidyas@...dia.com>
---
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index 48160f48003a..5007a2a8647c 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -155,7 +155,7 @@
nvidia,schmitt = <TEGRA_PIN_DISABLE>;
nvidia,lpdr = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
- nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
+ nvidia,io-hv = <TEGRA_PIN_ENABLE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
};
@@ -167,7 +167,7 @@
nvidia,schmitt = <TEGRA_PIN_DISABLE>;
nvidia,lpdr = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
- nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
+ nvidia,io-hv = <TEGRA_PIN_ENABLE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
};
--
2.17.1
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