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Message-Id: <20201026080127.40499-7-biwen.li@oss.nxp.com>
Date: Mon, 26 Oct 2020 16:01:23 +0800
From: Biwen Li <biwen.li@....nxp.com>
To: shawnguo@...nel.org, robh+dt@...nel.org, mark.rutland@....com,
leoyang.li@....com, zhiqiang.hou@....com, tglx@...utronix.de,
jason@...edaemon.net, maz@...nel.org
Cc: devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
jiafei.pan@....com, xiaobo.xie@....com,
linux-arm-kernel@...ts.infradead.org, Biwen Li <biwen.li@....com>
Subject: [RESEND 07/11] arm64: dts: ls208xa: add DT node for external interrupt lines
From: Biwen Li <biwen.li@....com>
Add device-tree node for external interrupt lines IRQ0-IRQ11.
Signed-off-by: Biwen Li <biwen.li@....com>
---
.../arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 33 ++++++++++++++++++-
1 file changed, 32 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
index 41102dacc2e1..f75aa2ce4e2b 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
@@ -3,7 +3,7 @@
* Device Tree Include file for Freescale Layerscape-2080A family SoC.
*
* Copyright 2016 Freescale Semiconductor, Inc.
- * Copyright 2017 NXP
+ * Copyright 2017-2020 NXP
*
* Abhimanyu Saini <abhimanyu.saini@....com>
*
@@ -154,6 +154,37 @@
little-endian;
};
+ isc: syscon@...0000 {
+ compatible = "fsl,ls2080a-isc", "syscon";
+ reg = <0x0 0x1f70000 0x0 0x10000>;
+ little-endian;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x1f70000 0x10000>;
+
+ extirq: interrupt-controller@14 {
+ compatible = "fsl,ls2080a-extirq", "fsl,ls1088a-extirq";
+ #interrupt-cells = <2>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x14 4>;
+ interrupt-map =
+ <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+ <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+ <8 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+ <11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map-mask = <0xffffffff 0x0>;
+ };
+ };
+
tmu: tmu@...0000 {
compatible = "fsl,qoriq-tmu";
reg = <0x0 0x1f80000 0x0 0x10000>;
--
2.17.1
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